SRM University 2007 B.Tech Electronics and Communications Engineering BANK : Microprocessor and Interfacing - Question Paper

28. List out the EOI command supported by 8259A.
29. Write down the improper command word data format to program 8259A
a. Non specific EOI command
b. Specific EOI command.
30. Write down the improper command word data format to program 8259A
a. Automatic rotation with AEOI=1.
b. To turn off the automatic rotation mode
31. Using the I/O mapped scheme, is it possible to address more than 256 i/p devices assuming that the total number of O/P devices is less than 256?
32. How do you program the IMR register in 8259A?
33. List out the various priority modes supported by 8259A.
34. Write down the data format of 8259A output when programmed in polling mode.
35. Explain polling mode of 8259A.
36. What is the difference ranging from fully nested mode and special fully nested mode of 8259A?
37. Explain fully nested mode of 8259A.
38. What is the difference ranging from automatic rotation mode and specific rotation mode?
39. What is the various ranging from special mask mode and masking interrupt using IMR?
40. Calculate the address lines needed for addressing
a. 8KB memory
b. 2 MB memory
41. Calculate the number of memory chips needed to design one MB memory if the memory chip size is 1024 X 4.
42. How many memory locations can be addressed by a microprocessor with 14 address lines?
43. Specify the number of memory cells and registers in a 128X4 memory chip.
44. How many bits are stored by a 256X4 memory chip? Can this chip be specified as 128 KB memory?
45. The memory map of a 4K byte memory chip starts at the location 2000H. Specify the address of the last location on the chip and the number of pages in the chip.
46. The memory address of the last location of a 1K byte memory chip is provided as FBFFH. Specify the starting address.
47. How many address lines are used to identify an I/O port in the peripheral I/O and in the memory mapped I/O methods?
48. List out the advantages and disadvantages of absolute & linear address decoding.
49. What are interfacing devices?
50. Assume that memory location 2075h has a data byte 47H, specify the contents of the address bus A15-A8 and the multiplexed bus AD7-AD) when microprocessor asserts the RD signal.
51. Explain why the number of output ports in the peripheral mapped I/O is restricted to 256 ports.
52. In the peripheral mapped I/O, can an input port and an output port have the identical port address?
53. Specify the 8085 signals that are used to latch data in an output port.
54. Specify the 8085 signals that are used to enable an input port.

Earning:   Approval pending.