SRM University 2007 B.Tech Electronics and Communications Engineering BANK : Microprocessor and Interfacing - Question Paper

15. Explain the external hardware synchronization instruction.
16. Explain the Bit manipulation instruction.
17. Draw the flag format and discuss every flag conditions.
18. Explain the register structure in 8086.
19. Write a program to move the string from 1 memory location to a different memory location.

UNIT III

Part – A
1. Define interrupt & polling.
2. Compare and contrast polling & interrupt
3. Discuss the need for interrupt structure in microprocessor?
4. In what way interrupts are classified in 8085?
5. Define a) Hardware interrupts b) Software interrupts
6. What are the hardware interrupts supported in 8085?
7. Name the software interrupts supported in 8085.
8. Which interrupt has the highest priority in 8085?
9. Define a) Maskable interrupts b) Non Maskable interrupts
10. Define a) vectored interrupts b) Non vectored interrupts
11. What is a)interrupt latency b) interrupt response time?
12. Which interrupt is not level sensitive in 8085?
13. Name the level triggering interrupts in 8085.
14. List the interrupt related instructions in 8085.
15. Is there a minimum pulse width needed for the INTR signal? If so, specify the duration.
16. How long can the INTR pulse stay high?
17. Can the microprocessor be interrupted again before the completion of the 1st interrupt service routine?
18. Write a program to enable all the interrupts in an 8085 system.
19. Write a program
a. to mask RST 5.5
b. to enable RST 6.5
20. What will happen to the interrupt system in 8085 when the processor is reset?
21. State actual or false
a. EI instruction is necessary to implement the TRAP interrupt, but external hardware and the SIM instruction are unnecessary.
b. Instruction RIM is used to disable the interrupts 7.5, 6.5, 5.5.
c. The execution of instructions MVI A,10H and SIM will enable all 3 RST instructions
22. Specify the function performed by
a. SIM
b. RIM instructions
23. List out the Restart instructions supported by 8085 and their vectored memory locations.
24. How do you mask INTR interrupt in 8085?
25. Explain the advantage of using PIC 8259A over priority encoder in connecting multiple interrupts with the INTR interrupt line.
26. Write an instruction sequence that will reason the priority of an 8259A whose even address is 8Ah to be IR4, IR5, IR6, IR6, IR7, IR0, IR1, IR2, IR3.
27. Write an instruction sequence that will mask the requests on IR3, IR4 & IR6 of 8259A whose even address is 66H .

Earning:   Approval pending.