Jawaharlal Nehru Technological University Hyderabad 2007 M.Tech Embedded Systems ANALOG AND DIGITAL IC DESIGN - Question Paper

M.Tech. I-Semester Examinations, February-2007.
ANALOG AND DIGITAL IC DESIGN
(Embedded Systems)
Time: three hours Max. Marks: 60
ans any 5 ques.
All ques. carry equal marks
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1.a) Sketch a simple CMOS current mirror together with a small signal model and discuss about its output impedances.
b) Derive an expression to show that the total output noise mean squared value is = f2)(rmsnoV2nwVx = (2nwV2?) f0
2.a) elaborate integrated filters? elaborate the draw backs of inductors?
b) discuss briefly about A Charge pump phase comparator.
3.a) Prove that the input impedance for this common gate amplifies is much larger than1/8m1.
b) What is parasitic sensitive integrator and discuss briefly?
4.a) elaborate the factors that affect gate – source voltage – explain?
b) discuss the importance of voltage controlled oscillators and how do you classify the oscillators.
5.a) discuss the term concurrent and sequential coding constructs with examples.
b) Write a VHDL model of 2n to n priority encoder.
6.a) Write a VHDL model of n bit parallel to serial converter.
b) elaborate the advantages and disadvantages of ripple counter with respect to synchronous counters?
7.a) Write a behaviour model of negative edge triggered D flip flop with set and clear.
b) Briefly discuss FPGA classification based on CLB arrangement.
8.a) Write short notes on:
a) CPLD Architectures
b) Flicker noise
c) ECL gate
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Earning:   Approval pending.