Jawaharlal Nehru Technological University Hyderabad 2007 M.Tech VLSI system design VHDL MODELING OF DIGITAL SYSTEMS - Question Paper

M.Tech. I-Semester Examinations, February-2007.
VHDL MODELING OF DIGITAL SYSTEMS
(VLSI System Design)
Time: three hours Max. Marks: 60
ans any 5 ques.
All ques. carry equal marks
- - -
1.a) After the synthesis stage in modeling a design using CAD tools,
how is physical design done?
b) Write a brief note on placement and Routing phase in the design of
a digital system using CAD tools.

2. List out the sequential statements in process statements. discuss
every 1 of them with an example.

3.a) Write a procedure to convert a multivalued kind from a array to an
integer.
b) discuss the terms package declaration and package body in VHDL.

4.a) Design a N-bit decoder with VHDL description using component
configuration statements.
b) discuss how generics can be specified in configurations to allow
late binding of generic info.

5.a) Write an overloading function for the operator+ that allows
addition of 2 objects of bit-vector kinds.
b) Write VHDL code for a BCD-to-7 segment code converter, using a
opted signal assignment.

6. Determine the functional behavior of the circuit provided beneath.
presume that the input w is driven by a square wave signal.

7. Derive the state diagram for an FSM that has an input w and an
output Z. The machine has to generate Z=1 when the previous
four values of w were 1001 or 1111 else Z=0. Overlapping input
trends are allowed. Write VHDL code for the above FSM.

8. Write short notes on Behavioral description of Para wan CPU.
^^^

Earning:   Approval pending.