Jawaharlal Nehru Technological University Hyderabad 2007 M.Tech VLSI system design DIGITAL SYSTEM DESIGN - Question Paper

Code No: 54111/MT
M.Tech. I-Semester Examinations, February-2007.
DIGITAL SYSTEM DESIGN
(Digital System and Computer Electronics, Digital Electronics and
Communication Systems, VLSI System Design)
Time: three hours Max. Marks: 60
ans any 5 ques.
All ques. carry equal marks
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1.a) What is a logic probe what for it is used and list various internal
digital IC faults?
b) elaborate the most common kind of external faults?

2.a) Develop an ASM chart of D flip flop and realize it using only NAND
Gates.
b) explain in detail about reduction of state tables and state
assignments.

3.a) discuss about the subsequent kinds of faults:
(i) stuck at faults (ii) Bridge faults (iii) temporary faults
b) Draw the circuit which realizes the function f(x) = x1x2 + x3 x4 using
AND-OR gates using Boolean difference method find the test set
to detect SAo fault on input line x1 of the circuit.

4.a) define the algorithmic steps involved in PODEM.
b) With an example, discuss the transition count testing method.

5.a) Distinguish ranging from Mealy and Moore machines.
b) Convert the subsequent Mealy machine into a corresponding Moore
machine.
PS
A B,O E,O
B E,O D,O
C D,I A,O
D C,I E,O
E B,O D,O

6.a) define the advantages of PLA minimization and folding.
b) Design a three bit BCD to grey code converter and realize the circuit
using PLA and then show that how folding will decrease the number
of cross points provided on the PLA.

7.a) With examples, discuss in detail about different kinds of cross point
fault that occur in PLAs.
b) With an example, discuss how test generation can be achieved in
testing a PLA.

8.a) discuss the subsequent with examples:
(i) flow table (ii) state reduction.
b) With respect to an asynchronous sequential machine, discuss
about minimal closed corners.
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Earning:   Approval pending.