Jawaharlal Nehru Technological University Hyderabad 2007 M.Tech VLSI system design LOW POWER VLSI DESIGN - Question Paper

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Code No: 54206/MT
M.Tech. II-Semester Examinations, August/September-2007.

LOW POWER VLSI DESIGN
(Embedded Systems, Digital Electronics & Communication Systems
and VLSI System Design)
Time: three hours Max. Marks: 60
ans any 5 ques.
All ques. carry equal marks
- - -

1.a] elaborate the different advantages and limitations of the Silicon–on-
Insulator Technology ?
b] discuss about shallow Trench Isolation (SIT) technique.

2.a] How threshold Voltage adjustments can be carried out for CMOS
devices? discuss with the help of necessary equations.
b] With the help of sketches discuss about the Retrograde–Well CMOS
process.

3. define the Low – Voltage, Low- power CMOS SOI process.

4.a] define the dynamic characteristics of MOS transistor, using
necessary equations.
b] define the characteristics of Secondary MOS FET behavior.

5. Draw the circuit for common–Emitter Bi CMOS driver
configuration and discuss its characteristics.

6. discuss about the characteristics of Bi CMOS
a] Circuits utilizing lateral p-n-p BJTs in PMOS structures.
b] provide the performance valuation of merged Bi CMOS logic gates.
How the weak points of conventional Bi CMOS logic gates are
overcome by these circuits ?

7.a] discuss about the Functionality Theme and Synchronous themes
of latches and Flip – Flops.
b] elaborate the Performance measures of latches and Flip–Flops.

8. Write notes on any 2
a] MOSFET in a Hybrid – mode environment.
b] ESD–free Bi CMOS
c] Bipolar SPICE Model

Earning:   Approval pending.