Jawaharlal Nehru Technological University Hyderabad 2007 M.Tech VLSI system design MODELLING AND SYNTHESIS WITH THE VERILOG HDL - Question Paper

M.Tech II-Semester Examinations, August/September-2007.
MODELLING AND SYNTHESIS WITH THE VERILOG HDL
(VLSI System Design)
Time : three hours Max. Marks : 60
ans any 5 ques.
All ques. carry equal marks
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1.a) discuss about (i) Initial Statement and (ii) Always statement giving examples in Verilog.
b) elaborate the 2 types of event controls in Verilog? discuss with examples.
2.a) What is the use of Block Statement in Verilog? elaborate the 2 types of Blocks in Verilog HDL? discuss with examples.
b) What is the statement in Verilog HDL to assign to only a register data type? provide an example.
3.a) elaborate the 4 types of loop statements in Verilog HDL? provide examples.
b) Write a sample program to discuss about the function of de assign statement.
4.a) Draw the logic circuit and discuss how a Variable is synthesized as a latch.
b) provide an example to show that variable GRADE is not a latch, when it is assigned a value in all branches of the IF statement.
5.a) define a combinational logic circuit in verilog HDL using continuous assignment statements and hence show that the synthesized logic is implicit in description.
b) Build a module for a memory and then instantiate in a synthesis model as a component using the module instantiation statement.
6. Draw the block schematic of a Mealy finite state machine. Using reg variable, model the state of the machine.
7. Using Verilog HDL, model a 2-by-2 binary multiplexer draw the logic circuit.
8. Write notes on any TWO:
a) Synthesis of edge Triggered Flip Flops
b) Synthesis of 3 state buffers.
c) Repeated Intra Assignment Delay.
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Earning:   Approval pending.