Jawaharlal Nehru Technological University Hyderabad 2010-2nd Sem M.Tech VLSI system design Regular s tember, ALGORITHMS FOR VLSI DESIGN AUTOMATION (COMMON TO DS AND CE, ) - Question Paper

Code No: B0609, B5701
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M.Tech II - Semester Regular exams September, 2010
ALGORITHMS FOR VLSI DESIGN AUTOMATION
(COMMON TO DS AND CE, VLSI SYSTEM DESIGN)
Time: 3hours Max. Marks: 60
ans any 5 ques.
All ques. carry equal marks
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1. (a) discuss the process of generic IC design methodology.
(b) discuss the term "Computational complexity" related to VLSI design automation.

2. (a) Write an algorithm for branch and bound method.
(b) provide an algorithm for an exhaustive search by means of back tracking.

3. (a) provide pseudo code description of simulated annealing.
(b) discuss about the Liao-Wong algorithm.

4. (a) What is meant by modeling and simulation ? discuss with an example.
(b) Distinguish ranging from gate level simulation and switch level simulation.

5. (a) discuss about 2 level logic synthesis with suitable example.
(b) discuss about binary-decision diagrams with an example.

6. (a) explain about high level transformations related to high level synthesis.
(b) discuss allocation and assignment related to high level synthesis.

7. (a) discuss about different FPGA technologies.
(b) What is the role of partitioning and routing for segmented and staggered models?
discuss.

8. Write short notes on the subsequent
(i) Chip array based approaches.
(ii) Multiple stage routing.
(iii) Intractable issues.

Earning:   Approval pending.