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Jawaharlal Nehru Technological University Hyderabad 2009-2nd Sem B.Tech Information Technology , Code No: 07A4EC13 Set No.2 II Regular s, COMPUTER ORGANIZATION ( Common to Computer Science

Thursday, 27 June 2013 11:30Web

Code No: 07A4EC13 Set No. 2
II B.Tech II Semester Regular Examinations, May 2009
COMPUTER ORGANIZATION
( Common to Computer Science & Engineering, info Technology,
Computer Science & Systems Engineering, Electronics & Computer
Engineering and Instrumentation & Control Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) discuss the terms compiler, linker, assembler, loader and define how a C
program or any other high level language program is executed in a system.
Indicate entire process with a figure.
(b) Distinguish ranging from high level and low level languages?. elaborate the re-
quirements for a good programming language? [16]
2. Design a circuit for parallel load operation into 1 of the 4 4-bit registers from
a bus. Mention clearly control/selection bits and selection logic. presume JK flip-
flops. [16]
3. (a) Support or oppose the statement. If we want to add a new machine language
instruction to a processors instruction set, simply write a C program and
compile and store the resulting code in control memory. [8]
(b) Why do we need subroutine register in a control unit? discuss. [8]
4. (a) Multiply 10111 with 10011 using, Booths algorithm. [8]
(b) discuss booths algorithm with its theoretical basis. [8]
5. (a) ”In paged segmentation, the reference time increases and fragmentation de-
creases”, Justify your ans.
(b) A Virtual Memory System has an address space of 8K words and a Memory
space of 4K words and page and block sizes of 1K words. Determine the
number of page faults for the subsequent page replacement algorithms: 1) FIFO
2) LRU if the reference string is as follows: 4,2,0,1,2,6,1,4,0,1,0,2,3,5,7. [8+8]
6. elaborate relative advantages and disadvantages of I/O communication techniques?
Explain. [16]
7. discuss array processors. discuss SIMD array processor organization in detail.
[16]
8. (a) discuss the functioning of omega switching network with a neat sketch. [8]
(b) In eight x eight omega switching network how many stages are there and in every stage
how many Switches are there. [4]
(c) How many stages and how many Switches in every stage are needed in a n x n
omega sitching network.


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