Jawaharlal Nehru Technological University Hyderabad 2009-2nd Sem B.Tech Information Technology , Code No: 07A4EC13 Set No.3 II Regular s, COMPUTER ORGANIZATION ( Common to Computer Science

Code No: 07A4EC13 Set No. 3
II B.Tech II Semester Regular Examinations, May 2009
COMPUTER ORGANIZATION
( Common to Computer Science & Engineering, info Technology,
Computer Science & Systems Engineering, Electronics & Computer
Engineering and Instrumentation & Control Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) elaborate the various interconnection structures used in multiprocessors?
discuss about multistage crossbar switch. [8]
(b) Support or oppose the statement ?Every efficient serial program is efficient
parallel program? [8]
2. Design a circuit for parallel load operation into 1 of the 4 4-bit registers from
a bus. Mention clearly control/selection bits and selection logic. presume RS flip-
flops. [16]
3. (a) elaborate the design goals for a designer while deciding a hardwired or micro-
programmed CU for a CPU? [8]
(b) discuss nanoinstructions and nanometry. Why do we need them. [8]
4. (a) discuss Booth’s algorithm with its theoretical basis. [8]
(b) Represent 2 n-bit unsigned numbers multiplications with a series of n/2-bit
multiplications. [8]
5. discuss two-way set associative mapping and four-way set associative mapping
techniques with an example for every. [16]
6. discuss the subsequent with respect to serial communication:
(a) Data Communication processor
(b) Modem
(c) Block Transfer
(d) CRC
(e) Full Duplex
(f) Bit oriented protocol. [3+3+2+3+2+3]
7. Write short notes on the following:
(a) Risc pipeline
(b) Vector processing
(c) Array processors.
8. (a) discuss multiport memory organization with a neat sketch.
(b) discuss system bus structure for multiprocessors with a neat sketch

Earning:   Approval pending.