Jawaharlal Nehru Technological University Hyderabad 2009-2nd Sem B.Tech Information Technology , Code No: 07A4EC13 Set No.4 II Regular s, COMPUTER ORGANIZATION ( Common to Computer Science

Code No: 07A4EC13 Set No. 4
II B.Tech II Semester Regular Examinations, May 2009
COMPUTER ORGANIZATION
( Common to Computer Science & Engineering, info Technology,
Computer Science & Systems Engineering, Electronics & Computer
Engineering and Instrumentation & Control Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) elaborate the various interconnection structures used in multiprocessors?
discuss about multistage crossbar switch. [8]
(b) Support or oppose the statement ?Every efficient serial program is efficient
parallel program? [8]
2. There exists 3 4-bit registers (A,B, and C) and 4-bit data lines (say D). Design
a circuit to transfer data from any register to any other register including data lines
and vice versa. [16]
3. (a) Differentiate ranging from microprogramming and nanoprogramming. [8]
(b) Hardwired control unit is faster than microprogammed control unit. Justify
this statement. [8]
4. discuss the computational errors. Why do they occur?. provide a few issues where
these errors are catastrophic. Also, provide a few practical examples (algorithms) where
fault gets
(a) accumulated and
(b) multiplies. [16]
5. (a) Compare and contrast FIFO and LRU Cache Replacement Algorithms.
(b) Compare and contrast direct and associative mapping Techniques. [8+8]
6. (a) What is Direct Memory Access? discuss the working of DMA.
(b) elaborate the various types of DMA transfers? discuss.
(c) elaborate the advantages of using DMA transfers? [8+4+4]
7. (a) What is meant by instruction pipeline? discuss 4 segment Instruction
Pipeline.
(b) provide the timing diagram of instruction pipeline. [8+8]
8. (a) discuss serial abitration (Daisy Chain).
(b) discuss prallel abitration.

Earning:   Approval pending.