Rashtrasant Tukadoji Maharaj Nagpur University 2009 B.E Electronics & Communication Engineering Summer , Faculty of Engineering and Technology, COMPUTER ORGANISATION - Question Paper

part A

1. discuss prototype structure, performance measurement and queuing models steps of processor level design.

2. (a) Mutiply using Booths algorithm:
(i) -13*12
(ii) 14*-9
(b) define the IEEE 754 standard floating point number format with suitable example.

3. (a) With suitable example, discuss the different addressing modes. provide significance importance of every.
(b) Using non-restoring method solve: 9/4

4. (a) discuss the following:
(i) Control memory
(ii) Micro program
(iii) Emulator
(iv) Micro-assembler
(b) discuss in brief Bit Sliced ALU.

5. Write short notes on any THREE:
(i) Hardwired control
(ii) Micro instruction sequencing
(iii) Co processors
(iv) Array processors.

part B

6. discuss in detail address mapping techniques used in Cache memory giving suitable memory of every.

7. (a) List the various characteristics of a memory device.
(b) Design a 4K*8 bits RAM using 1K*2 bits RAM.

8. (a) What is bus arbitration? discuss polling scheme for bus arbitration.
(b) discuss the concept and advantages of parallel processing with improper example.

9. (a) discuss the process of DMA data transfer.
(b) Briefly define local and long distance communication.
(c) What is meant by "Cycle stealing"?

10. Write short notes on:
(i) Vector processor
(ii) Risc processor
(iii) I/O processor.

Earning:   Approval pending.