Jawaharlal Nehru Technological University Hyderabad 2005-1st Sem B.E Computer Science COMPUTER ORGANIZATION III B.TechSupplementary s,set 2 - Question Paper

Code No: RR321301 Set No. 2
III B.Tech I Semester Supplementary Examinations,
November/December 2005
COMPUTER ORGANIZATION
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) Draw and discuss the timing of learn operation in both synchronous
and asynchronous timing.
(b) explain different data transfer kinds supported by buses
[8+8]
2. (a) obtain the output binary number after performing the subsequent
arithmetic operations
i. 111.01 + 10.111
ii. 11.01 + 110.11
iii. 110.11 111.01
(b) discuss about the longhand division of binary integers.
[6+10]
3. explain different key design problems of an instruction format.
[16]
4. (a) List and define various Motorola 88000 bitfield
instructions.
(b) explain about register management in Motorola 88000
[8+8]
5. (a) discuss any 3 replacement algorithms with examples.
(b) explain in detail about set associative mapping in cache memory.
[8+8]
6. explain about data organization and formatting of magnetic disk in detail
[16]
7. (a) Differentiate ranging from micro programmed and hard wired control units
with merits and demerits of every.
(b) explain about the design considerations of micro instruction
sequencing technique.
[8+8]
8. (a) Why special handling is needed for branch instruction in a pipelined
processor. discuss with examples.
(b) How would you determine the number of pipeline stages in a
pipelined processor
[10+6]
? ? ? ? ?

Earning:   Approval pending.