Jawaharlal Nehru Technological University Hyderabad 2005-1st Sem B.E Computer Science COMPUTER ORGANIZATION III B.TechSupplementary s,set 3 - Question Paper

Code No: RR321301 Set No. 3
III B.Tech I Semester Supplementary Examinations,
November/December 2005
COMPUTER ORGANIZATION
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. discuss about VonNeumann architecture design in detail.
[16]
2. (a) obtain the output binary number after performing the arithmatic
operation using 1’s complement representation.
i. 111.01 + 10.111
ii. 110.11 111.01
(b) discuss steps involved in the addition of numbers using 2’s
complement notation.
[10+6]
3. discuss different power PC addressing modes with algorithms
[16]
4. (a) List and define different coprocessor
and special instructions of
MIPS Rseries
processors.
(b) Differentiate ranging from theoretical R3000 and true R4000 super
pipelines.
[10+6]
5. (a) discuss any 3 replacement algorithms with examples.
(b) explain in detail about set associative mapping in cache memory.
[8+8]
6. (a) discuss how bus arbitration is done in DMA transfer
(b) explain about the generic model of an I/O module.
[8+8]
7. (a) On which kinds of information, a conditional branch instruction
depends?
(b) discuss about IBM 3033 control address register
(c) explain about characteristics and terminology of microinstruction
spectrum [5+5+6]
8. (a) Why special handling is needed for branch instruction in a pipelined
processor. discuss with examples.
(b) How would you determine the number of pipeline stages in a
pipelined processor
[10+6]
? ? ? ? ?

Earning:   Approval pending.