Jawaharlal Nehru Technological University Hyderabad 2006-2nd Sem B.E Computer Science COMPUTER ORGANISATION II B.TechRegular s, / set 1 - Question Paper

Code No: RR220501 Set No.1
II B.Tech II Semester Regular Examinations, Apr/May 2006
COMPUTER ORGANIZATION
(Common to Computer Science & Engineering, info Technology,
Computer Science & Systems Engineering and Electronics & Computer
Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) How mandatory signal lines for PCI are functionally grouped
(b) discuss typical desktop system using PCI configuration.
[8+8]
2. (a) How subtraction is done on the binary numbers represented in one’s
complement notation provide an examples.
(b) What do you mean by r’s complement?
[8+8]
3. discuss common addressing modes with suitable flow diagrams. Also
discuss the merits and demerits of each, in detail.
[16]
4. (a) discuss the register organization in a Power PC processor
(b) Classify interrupts on a Power PC.
[8+8]
5. (a) discuss different schemes available for partitioning memory and the
merits and demerits of every.
(b) What is compaction?
(c) Differentiate ranging from external and internal fragmentation
[8+3+5]
6. (a) What is the transfer rate for 9track
magnetic tape unit whose tape
speed is 120 inches per 2nd and whose tape density is 1600 linear
bits per inch?
(b) what are about erasable optical disk
(c) Differentiate ranging from sequentialaccess
and directaccess
devices
[8+4+4]
7. (a) How the address of next microinstruction is known while executing a
microprogram.
(b) explain about branch control logic in microinstruction sequencing
with variable address format. [6+10]
8. A pipelined processor has 2 branch delay slots. An optimizing complier
can fill 1 of these slots 85 percent of the time and can fil 2nd slot
only 20 percent of the time. What is the percentage improvement in
performance achieved by this optimization?
[16]
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Earning:   Approval pending.