Jawaharlal Nehru Technological University Hyderabad 2006-2nd Sem B.E Computer Science COMPUTER ORGANISATION II B.TechRegular s, / set 3 - Question Paper

Code No: RR220501 Set No. 3
II B.Tech II Semester Regular Examinations, Apr/May 2006
COMPUTER ORGANIZATION
(Common to Computer Science & Engineering, info Technology,
Computer Science & Systems Engineering and Electronics & Computer
Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
? ? ? ? ?
1. (a) Differentiate ranging from dedicated and multiplexed bus lines.
(b) explain different methods of bus arbitration.
(c) What do you mean by bus width?
[5+7+4]
2. (a) discuss about the arithmetic in excess 3
code.
(b) explain about normalized floating point representation
[6+10]
3. (a) List the instruction formats used on the PDP11.
(b) Draw and discuss Pentium instruction format.
[8+8]
4. what are on various kinds of registers in a register organization
[16]
5. (a) explain the principles of associative memory.
(b) discuss the functioning of four x four bit associative memory array.
(c) discuss the cache with twoway
setassociative
addressing
[6+4+6]
6. (a) What is the transfer rate for 9track
magnetic tape unit whose tape
speed is 120 inches per 2nd and whose tape density is 1600 linear
bits per inch?
(b) what are about erasable optical disk
(c) Differentiate ranging from sequentialaccess
and directaccess
devices
[8+4+4]
7. (a) discuss the principles and working of dot matrix printers.
(b) Differentiate ranging from various kinds of printers.
[8+8]
8. (a) Why special handling is needed for branch instruction in a pipelined
processor. discuss with examples.
(b) How would you determine the number of pipeline stages in a
pipelined processor
[10+6]
? ? ? ? ?

Earning:   Approval pending.