# Institute of Chartered Financial Analysts of India (ICFAI) University 2006 B.E Computer Architecture - exam paper

Monday, 17 June 2013 09:30Web

Note : Attempt any three ques. in all. Q1 is compulsory. every ques. carries 10 marks.

**Time :**11/2 Hours

**Maximum Marks**: 30

Computer Architecture

Q1

( a )

How many bits wide memory addresses have to be if the computer had 16 MB of memory? (Use the smallest value possible)

1

( b )

Derive the accurate floating point representation of the decimal numbers +3.5 and -2.1 using the 32 bit IEEE 754 floating point standar

**d.**2

( c ) Consider the subsequent floating points:

Mantissa of X = 110011, Exponent of X = 1100111

Mantissa of Y = 000001, Exponent of Y = 1101111

Perform operations X + Y. 1.5

( d ) Differentiate ranging from Selective repeat Set and Selective Compliment. 2

( e ) The subsequent transfer statements specify a memory. discuss the memory operation in every case

**i)**R2 <- M[AR]

**i**M[AR] <- R3 1.5

**i)**( f ) Differentiate ranging from Classical method and 1 Hot method of Control Design. 1.5

Q2

( a )

Design an arithmetic circuit with 1 selection input S and 2 n-bit data inputs A and

**B.**The circuit generates the subsequent 4 arithmetic operations:

S Cin=0 Cin=1

0 D = A + one D = A + B

1 D = A + B + one D = A - 1

1 + 4*1

( b )

A digital computer has a common bus system for 12 registers of nine bits every. The bus is constructed with multiplexers.

1.

How many selection inputs are there in every multiplexer? [1]

2.

What size of multiplexers are needed? [1]

3.

How many multiplexers are there in the bus? [1]

4.

Draw a diagram of the bus system using three-state buffers and a decoder instead of multiplexers? [2]

Q3

( a )

The system uses a control memory of 1024 words of 32 bits every. The microinstruction has 3 fields for micro-operations. choose a status bit and Brach address fiel

**d.**The micro-operation field has 16 bits.

**1.**How many bits are there in the branch address field and choose field?

**2.**If there are 16 status bits in the system, how many bits of the branch logic are used to choose a status bit?

**3.**How many bits are left to choose the input to the multiplexers?

2+2+1

( b )

The contents of the PC in the basic computer is 3AF (all numbers in HEX). The contents of AC are 7EC

**3.**The contents of memory at address 3AF are 09A

**C.**The contents of memory at address 9AC is 8B9

**F.**presume op-code 001 stands for ADD operation.

**1.**What is the instruction that will be fetched and executed next?

**2.**Show the binary operation that will be performed?

**3.**provide the contents of registers PC, AR, DR, AC and IR in hexadecimal at the end of the instruction cycle.

0.5 +

0.5 +

4

Q4

( a )

Write a program to evaluate the arithmetic statement:

**1.**Using a general register computer with 3 address instructions.

**2.**Using an accumulator kind computer with 2 address instructions.

**3.**Using an accumulator kind computer with 1 address instructions.

**4.**Using a stack organized computer with zero address instructions.

5

( b )

A 2 word instruction is stored in memory at an address designated by the symbol W. The address field of the instruction (stored at W+

**1)**is designated by the symbol Y. The operand used during the execution of the instruction is stored at an address symbolized by Z. An index register contains the value

**X.**State how Z is computed from the other addresses if the addressing mode of the instruction is: (Give explanation also)

**1.**Direct

**2.**Indirect

**3.**Relative

**4.**Indexed

**5.**Immediate

Earning: Approval pending. |