DOEACC Society 2006 DOEACC C Level Computer Organization ( ) - Question Paper

B) a • ( b + c)
C) a' • ( b' + c')
D) (a' + b') • (a' + c')
C1-R3 Page three of five January, 2006
2. every statement beneath is either actual or FALSE. select the most improper one
and ENTER in the “tear-off” sheet attached to the ques. paper, subsequent
instructions therein. (1 x 10)
2.1 A high-level language program is converted to the executable form by the compiler itself.
2.2 A negative number has identical representation in signed-magnitude, signed 1’s
complement and signed 2’s complement forms.
2.3 In Booth’s algorithm, numbers in 2’s complement are multiplied along with their sign bits.
2.4 In virtual memory management, physical addresses are mapped to logical addresses.
2.5 x + y • z = (x + y) • (x + z) is actual in Boolean algebra.
2.6 An instruction pipeline operates on a stream of instructions by overlapping the phases of
instruction cycle.
2.7 A race condition is not possible in combinational circuits.
2.8 Zero cannot be normalized.
2.9 In content addressable memories all the words in the memory are compared
simultaneously.
2.10 Retrieving instruction from the memory is the instruction cycle.
3. Match words and phrases in column X with the nearest related meaning/
word(s)/phrase(s) in column Y. Enter your selection in the “tear-off” ans sheet
attached to the ques. paper, subsequent instructions therein. (1 x 10)
X Y
3.1 Single Output Line A. von Neumann
3.2 Self complementing code B. Programmed Control Transfer
3.3 Indirect Address C. BSA
3.4 Stored program concept D. Multiplexer
3.5 CPU checking I/O flag E. 2421
3.6 Subroutine call F. Odd function
3.7 Bracket less expression G. M[AR]
3.8 Simple instructions computer H. BCD
3.9 Zero address instructions I. Decoder
3.10 Multiple variable exclusive –OR J. Interrupt driven transfer
K. M[M[AR]]
L. Prefix
M. BUN
N. Risc
O. ISZ
P. Stack Organized Computer
Q. Infix
R. Even function
S. Cisc
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4. every statement beneath has a blank space to fit 1 of the word(s) or phrase(s) in
the list beneath. Enter your option in the “tear-off” ans sheet attached to the
ques. paper, subsequent instructions therein. (1 x 10)
A. AR B. 1st C. Adders
D. Two’s Complement E. Sequential F. Serial
G. Stored Program H. Virtual I. IR
J. Combinational K. Subtractor L. Second
M. Memory mapped N. One’s Complement O. Primary
P. PC Q. Locality of reference R. Parallel
S. ROM T. Isolated U. Magnetic tape
4.1 In 2 pass assembler, the address symbol table is generated in ________ pass.
4.2 An adder-subtractor single unit can be designed using full ________ and XOR gates.
4.3 A(n) ________ circuit can be defined using truth table.
4.4 The carry out of the most significant bit is discarded during addition of 2 numbers in
________ form.
4.5 CPU register storing the address of next instruction to be executed is ________.
4.6 Having identical read/write instructions for memory and I/O addresses is ________ I/O
concept.
4.7 High hit ratio of cache memory is possible because of ________.
4.8 In ________ memory management, there is no need to have entire program in the
primary memory.
4.9 In daisy-chaining priority method, all the devices that can request an interrupt are
connected in ________.
4.10 A(n) ________ is a random access device.
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PART TWO
(Answer any 4 questions)
5.
a) A computer uses a memory unit with 128MB words of 64 bits every. A binary instruction
code is stored in 1 word of memory. The instruction has 4 parts – a few bits to
differentiate ranging from 1 of the 4 addressing modes supported by the system, an
operation code, a register code part to specify 1 of the 512 registers and an address
part. Draw the instruction word format and indicate the number of bits in every part.
b) What disadvantage of strobe control method of data transfer does the handshaking
protocol overcome and how?
c) Briefly define the working of DMA.
(4+5+6)
6. A minority function is desired to be generated in a combinatorial circuit. The output
should be one when the number of 1’s is less than the number of 0’s in the input. The
output should be 0 otherwise. Design a four input minority function. Draw the circuit also.
(15)
7.
a) Using a stack organized computer with zero-address operation instructions, write a
program to evaluate the arithmetic statement
F G H
X A B C D E
*
* ( )
-
= + - +
b) List at lowest 3 differences ranging from a branch, a subroutine call and an interrupt.
(9+6)
8.
a) Write a subroutine in assembly language to compare 2 words for equality.
b) Consider a computer with virtual memory having 4 frames/block and 8 pages.
Through diagrams show how many page faults will occur with the reference string 0, 1,
7, 2, 3, 2, 7, 1, 0, three if page replacement policies used are (i) 1st In 1st Out (ii) lowest
Recently Used.
(7+8)
9.
a) Draw the flowchart to perform the subtraction of 2 numbers in signed magnitude form.
b) An instruction is stored at location 100 with its address field at location 101. The address
field has the value 600. The value at location 600 is 400, at 900 is 300 and at 400 is 200.
A processor register R1 contains the number 300. Evaluate the effective address and
the operand if the addressing mode of instruction is
i) indirect
ii) direct
iii) immediate
iv) indexed with R1 as index register.
Also diagrammatically show the contents of the part of the memory according to the data
provided above.
(9+6)
C1-R3 Page six of five January, 2006

Earning:   Approval pending.