DOEACC Society 2006 DOEACC C Level C13 Digital System Design ( ) - Question Paper

C13-R3: DIGITAL SYSTEM DESIGN
NOTE:
Time: three Hours Total Marks: 100
1.
a) What is multiplexer? Justify whether a multiplexer is sufficient to realize any Boolean
function.
b) Simplify the subsequent Boolean expression, and also find the simplified expression in
POSs form.
F = (C+D)¢ + A¢CD¢ + AB¢C¢ + A¢B¢CD + ACD¢
c) Realize a 3-input XOR gate with the help of 2-input NAND gates only.
d) Relatively compare the advantages and disadvantages of synchronous counter and
asynchronous counter.
e) Differentiate demultiplexer from decoder.
f) What is ripple counter? “Ripple counter is also known as divided-by-n counter.” -
Explain.
g) find a clocked T flip-flop using a clocked D flip-flop as basic unit.
(7x4)
2.
a) Draw a logic circuit of a 4-bit shift register with the help of JK flip-flops and multiplexers
having the facilities of (i) parallel loading, (ii) right shifting, (iii) left shifting, and (iv) no
change. Clearly state how are the facilities achieved.
b) Design a clocked JK flip-flop using only NAND gates.
c) describe race issue. What do you mean by race-around condition? Devise a
mechanism to resolve it and clearly state how it operates.
(6+6+6)
3.
a) State Shannon’s Expansion Theorem, and prove it.
b) describe minterm and maxterm. provide an example of every. State their significance, and
discuss why they are so called.
c) Suppose a decade counter is used to count down from nine through 0. Design a
combinational circuit, using only basic gates, that is to be appended after the decade
counter, so that the overall circuitry behaves like a down counter.
(6+6+6)
4.
a) Prove that NAND and NOR gates are universal logic gates.
b) define the general structure of CMOS logic circuit. find the transistor level circuit of
CMOS 3-input OR gate.
c) Design a CMOS circuit for the full adder, where (i) An, Bn, and Cn are 3 input
variables, (ii) Output carry Cn+1 is a function of An, Bn, and Cn, and (iii) Output sum Sn is a
function of An, Bn, Cn, and Cn+1.
(4+6+8)
C13-R3 Page one of two January, 2006
1. ans ques. one and any 4 ques. from two to 7.
2. Parts of the identical ques. should be answered together and in the identical
sequence.
5.
a) A synchronous counter with 4 JK flip-flops has the subsequent connections.
JA = KA =1,
JB = QA×QD¢, KB = QA,
JC = KC = QA×QB,
JD = QA×QB×QC, and KD = QA
Determine the modulus, n of the counter, and draw the output waveforms of the identical.
b) Realize the CMOS circuit with its structural specification as provided beneath. The circuit
consists of 4 transistors in series, 2 consecutive pMOS transistors Q1 and Q2 with
the source of Q1 as VDD, 2 consecutive nMOS transistors Q3 and Q4 with the source of
Q4 as grounded, and the output at the common drain of Q2 and Q3. In addition, the gates
of Q1 and Q4 are common to input 1, whereas the gates of Q2 and Q3 are complementary
to every other, with the gate of Q2 as input 2.
c) Draw the circuit diagram of a three-input totem-pole output TTL NAND gate. State with
justification whether 2 or more totem-pole outputs can be wire-ANDed.
(9+5+4)
6.
a) Design a serial two’s complementer circuit using JK flip-flop as the basic memory
element.
b) What is PLD? Write a short note on PLA folding.
c) Mention the advantages and disadvantages of Gate Array design style over Custom (or
Semi-Custom) design style, in designing VLSI chips.
(7+5+6)
7.
a) Construct a sequence generator to produce the sequence 11010110.
b) Design a synchronous counter using JK flip-flops to count the sequence:
“1-3-15-5-8-2-0-12-6-9”
c) Write a short note on Data flow modeling of VHDL.
(6+8+4)
C13-R3 Page two of two January, 2006

Earning:   Approval pending.