DOEACC Society 2006 DOEACC C Level CE1 - Advanced Computer Architecture( ) - Question Paper

CE1-R3: ADVANCED COMPUTER ARCHITECTURE
NOTE:
Time: three Hours Total Marks: 100
1.
a) explain 2 areas of computer design where pipelining is improper.
b) provide (at lowest four) major characteristics of a systolic array processor.
c) elaborate the possible ways of organizing the operating system of a multiprocessor to
meet its objectives?
d) Consider the subsequent FORTRAN DO loop:
SUM=0
DO 10 I=1, 1000, 1
10 SUM = SUM + B(I)
Perform a few modification to achieve speedup.
e) elaborate various kinds of pipeline hazards?
f) elaborate the factors to be considered in deciding cache size?
g) Outline a few specific properties of Risc systems.
(7x4)
2.
a) discuss the concept of pipelining in superscalar processors.
b) What is dynamic branch-prediction? explain 1 dynamic branch prediction scheme.
c) elaborate branch-target buffers? discuss with an example.
d) Determine the total branch penalty for a branch-target buffer assuming the penalty cycles
for individuals mispredictions from the subsequent table.
Instruction in buffer Prediction true branch Penalty cycles
yes taken taken 0
yes taken not taken 2
No taken 2
No not taken 0
Make the subsequent assumptions about the predictions about the prediction accuracy and
hit rate:
? Prediction accuracy is 90% (for instructions in the buffer).
? Hit rate in the buffer is 90% (for branches predicted taken).
presume that 60% of the branches are taken.
(3+5+4+6)
3.
a) explain various software approaches used to exploit instruction level parallelism.
b) Consider a loop like the 1 below:
for (i=1; i<=100; i=i+1) {
A[i+1] = A[i] + C[i]; /*S1*/
B[i+1] = B[i] + A[i+1]; /*S2*/
CE1-R3 Page one of three January, 2006
1. ans ques. one and any 4 ques. from two to 7.
2. Parts of the identical ques. should be answered together and in the identical
sequence.
presume that A,B, and C are distinct, nonoverlapping arrays. elaborate the data
dependences among the statements S1 and S2 in the loop?
c) Consider a loop like this one:
for (i = 1; i<=100; i=i+1) {
A[i] = A[i] + B[i]; /*S1*/
B[i+1] = C[i] + D[i]; /*S2*/
}
elaborate the dependences ranging from S1 and S2? Is this loop parallel? If not, Show how to
make it parallel.
d) The subsequent loop has multiple kinds of dependences. obtain all the actual dependences,
output dependences, and antidependences, and eliminate the output dependences and
antidependences by renaming.
for (i = 1; i<=100; i = i+1) {
Y[i] = X[i] / c; /*S1*/
X[i] = X[i] +c; /*S2*/
Z[i] = Y[i] +c; /*S3*/
Y[i] = c – Y[i]; /*S4*/
}
(3+4+5+6)
4.
a) presume we have a computer where the clock per instruction (CPI) is 1.0 when all
memory accesses hit in the cache. The only data accesses are loads and stores, and

Earning:   Approval pending.