DOEACC Society 2006 DOEACC C Level C13 Digital System Design ( ) - Question Paper

C13-R3: DIGITAL SYSTEM DESIGN
NOTE:
Time: three Hours Total Marks: 100
1.
a) Show that a positive logic NAND gate is a negative logic NOR gate and vice versa.
b) Show an implementation of the Equality comparator of 2 2-bit vectors using a network
of two input multiplexers.
c) discuss Parallel input Unidirectional Shift register with Load and Shift control.
d) discuss how Wired Logic can be implemented in TTL family.
e) Differentiate ranging from MOS and Junction transistor.
f) define a Schottky TTL gate by giving an improper diagram.
g) Differentiate ranging from behavioral and dataflow modeling in terms of Signal assignments.
(7x4)
2.
a) Design a minimal two-level gate combinational network that detects the presence of any
of the 6 illegal groups in the 8421 code by providing a logic-1 output.
b) Realize subsequent function with a three to eight line decoder + gates.
F1(x2,x1,x0) = p M(0,3,5)
F2(x2,x1,x0) = p M(2,3,4)
c) define depletion and enhancement mode devices. Show the use of MOSFET as
Resistor.
(6+6+6)
3.
a) Using a four bit binary adder, design a network to convert a decimal digit in excess-3 code
into a decimal digit in 8421 codes.
b) Derive PLA program table for a combinational circuit that squares a 3-bit number.
Minimize the number of product terms.
(9+9)
4.
a) Design up-down counter using J-K flip-flops.
b) What do you mean by lock-out of a counter? How do you test for the issue of lock-out
of a counter? How do you eliminate this problem?
c) What is Race Around problem? How is it handled in Master-Slave J-K flip-flop?
(8+6+4)
5.
a) Design a Sequence detector which detects subsequent binary sequence: 0 one 1 0 one 0
b) Design a sequential circuit defined by the subsequent state equations. Use JK flip-flops.
A(t+1) = xAB + yA'C + xy
B(t+1) = xAC + y'BC'
C(t+1) = x'B + yAB'
(9+9)
6.
a) explain the usage of packages & libraries and their binding in VHDL.
b) Write a VHDL code for 16 X eight bit memory with address, data, learn /write, enable inputs.
C13-R3 Page one of two July, 2006
1. ans ques. one and any 4 ques. from two to 7.
2. Parts of the identical ques. should be answered together and in the identical
sequence.
(9+9)
C13-R3 Page two of two July, 2006
7.
a) Write a VHDL code for Universal shift register with Parallel load facility. Use any of three
modeling.
b) library ieee;
use ieee.std_logic_1164.all;
entity module1 is
port( l,r,s1: in std_logic;
q: out std_logic_vector(3 downto 0);
s2: out std_logic);
end module1;
architecture behave of module1 is
signal f: std_logic_vector(3 downto 0);
begin
process(r,l)
if(r = ‘1’) then
f <= “0000”;
elsif (l’event and (l= ‘1’) ) then
f <= f(2 downto 0) & s1;
end if;
end process;
q <= f;
s2 <= f(3);
end behave;
i) Draw a black box of VHDL module for above code and explain actions
performed.
ii) Simulate the waveform of the above code.
(9+9)
C13-R3 Page three of two July, 2006

Earning:   Approval pending.