DOEACC Society 2006 DOEACC C Level CE1 - Advanced Computer Architecture( ) - Question Paper

CE1-R3: ADVANCED COMPUTER ARCHITECTURE
NOTE:
Time: three Hours Total Marks: 100
1.
a) Comment on the guidelines to convert any blocking multi-stage interconnection network
to its equivalent non-blocking counterpart.
b) Briefly comment on the major reasons for cache coherence issue in any
multiprocessor system?
c) describe diameter with respect to static networks.
d) elaborate the characteristics of SIMD architecture?
e) Comment on the number and kind of process states of any message passing system in
a multiprocessor system.
f) What factors determine the performance of vector processors?
g) Estimate the effect of branch instructions on the performance of pipelined architectures
with suitable set of parameters.
(7x4)
2.
a) presume that an unpipelined machine has 10-ns clock cycle and it uses four cycles every for
ALU operations and branch instructions and five cycles for memory operations. presume
that the relative frequencies of these operations are 40%, 20% and 40% respectively.
Suppose that due to clock skew and setup, pipelining the machine adds one ns overhead
to the clock. Ignoring any latency impact, how much speedup in the instruction execution
rate will be gained from a pipeline?
b) From a provided reservation table of a pipelined architecture (uni-function), how will obtain the
minimal and maximal values of avg. latencies? Justify your ans
(6+12)
3. What is meant by cache-coherency? discuss with the help of a suitable example. State
any 3 techniques to decrease cache miss. How does two-level cache increase
performance? Derive the formula for avg. access time in a three-level cache?
([3+2+6+4+3])
4.
a) What is a vector processor? elaborate the properties of vector instructions? How are the
two important problems like Vector Length and Stride tackled?
b) Vectorizing compilers generally detect loops that can be executed on a pipelined vector
computer. Are the vectorization algorithms used by vectorizing compilers suitable for
MIMD machine parallelization? Justify your ans.
(12+6)
CE1-R3 Page one of two July, 2006
1. ans ques. one and any 4 ques. from two to 7.
2. Parts of the identical ques. should be answered together and in the identical
sequence.
5.
a) discuss the various kinds of dependences among instructions with suitable examples.
b) Consider the subsequent loop:
for (i = 1; i <= 500; i++) {
A[i] = A[i] +B[i]; /* Statement one or S1 */
B[i+1] = C[i] +D[i]; /* Statement two or S2 */
}
elaborate the dependences ranging from S1 and S2? Is this loop parallel? If not, show how
to make it parallel.
(10+8)
6.
a) How is a block obtained if it is in cache? elaborate the various write policies for cache?
b) presume the subsequent miss rates:
Size Instruction Cache Data Cache Unified Cache
16 KB 0.64% 6.47% 2.87%
32 KB 0.39% 4.82% 1.99%
Which has the lower miss rate: a 16-KB instruction cache with a 16-KB data cache or a
32-KB unified cache? presume a hit takes one clock cycle and the miss penalty is 50 clock
cycles, and a load or store hit takes one extra clock cycle on a unified cache. What kind of
hazard the unified cache poses? What is the avg. memory access time in every
case? presume write-through caches with write buffer and ignore the difficulties due to
hazard.
(10+8)
7.
a) elaborate dynamic networks? elaborate the characteristics of access time in such
networks? What is Multistage Interconnection Network?
b) What do you mean by hazard? elaborate various kinds of hazards? elaborate the
option techniques to decrease the data hazard?
(9+9)
CE1-R3 Page two of two July, 2006

Earning:   Approval pending.