DOEACC Society 2007 Advanced Level Course In Computer Science A4-R3: COMPUTER ORGANIZATION - Question Paper

A. One B. Two C. State table
D. 64 bit data bus E. Indirect F. Three adjacent bits
G. Enable Interrupt H. 64 bit address I. User level
J. One of the two K. System level L. Data input
M. One clock N. Different clocks O. Both
P. Direct Q, Two adjacent bits R. Data output

4.1 A 64 bit microprocessor has _________.
4.2 It is desirable to make hit ratio is close to _________ as possible.
4.3 A Finite State Machine can be represented by _________.
4.4 Modified Booth algorithm examines _________ of the multiplier at a time.
4.5 CPU recognizes an interrupt if _________ instruction is executed.
4.6 In a register transfer instruction op code provides the address of _________ registers.
4.7 Assembler is a(n) _________ program, which translates assembly language program to machine language
4.8 A decoder can function as demultiplexer with enable input used as _________.
4.9 Synchronous IO transfer schemes operate from _________.
4.10 A memory reference register contains the address for the _________ addressing.






























PART TWO
(Answer any 4 questions)

5. Show how can an 8 input multiplexer be constructed from 2 input multiplexers. The 2 input multiplexer has enable input in addition to choose inputs. Draw diagram of the constructed multiplexer with suitable tags.
(15)

6. Give an algorithm for nonrestoring division for unsigned numbers.
(15)

7. State 2 limitations of Programmed IO method of data transfer scheme. How are these limitations eliminated in DMA? discuss this method with the help of basic diagram showing CPU, Memory and DMA controller connectivity. The DMA block in the diagram is to be drawn with its essential components.
(15)

8.
a) Calculate the avg. latency and the data-transfer rate of a moving-arm disk-storage device that has 200 tracks per recording surface, 2400 rpm and 62,500 bits track storage capacity.
b) Construct a 1M x 16-bit memory having 4 memory banks with four-way address interleaving. Identify the bank to which every of the subsequent hex encoded addresses is assigned.
i) 0123
ii) ABCDE
(7+8)

9. Write a assembly language program to add 2 16-bit numbers on 8-bit processor, 8085 (say).
(15)

A4-R3: COMPUTER ORGANIZATION

NOTE:
1. There are 2 PARTS in this Module/paper. PART 1 contains 4 ques. and PART 2 contains 4 ques..

2. PART 1 is to be answered in the TEAR-OFFANSWER SHEET only, attached to the ques. paper, as per the instructions contained therein. PART 1 is NOT to be answered in the ans book.

Earning:   Approval pending.