How To Exam?

a knowledge trading engine...


Visvesvaraya Technological University (VTU) 2005 B.E Electrical and Electronics Engineering 3rd Y/UST LOGIC DESIGN - Question Paper

Wednesday, 12 June 2013 05:55Web



NEW SCHEME



CS33


Page No... 7


v\*


'V vv>


USN


fhird Semester B.E. Degree Examination, July/August 2005

Common to BM/EC/EE/TE/ML/IT/CS/IS


Logic Design


{Max.Marks : 100


Time: 3 hrs.]


Note: Answer any FIVE full questions


1. (a) Explain Deinorgan's theorems in Boolean Algebra, (b) State and explain two applications of shift register.


(4 Marks) (6 Marks)


(c) Design a combinational circuit for 3 bit even-parity generator and implement it using NAND gates only.        do Marks)


2. (a) Design BCD to Excess 3 code converter using NOR gates only.


(8 Marks)


(b) What is race around condition? Explain how it is eliminated using J-K master-slave flip-flop.

(12 Marks)

Msing Quine Me Clusky tabulation method/ obtain the set of prime implicants for the function


d>.


\ 4


/(fl,6,c,d) = X:(0,l,4,5l9,10,12l14,15)+ 0(2,8,13)

and hence obtain the minimal form of the given function employing decimal representation.    -    (12 Marks)

(b) Design mod-4 ripple up counter with initial state is (011 )2 Draw timing diagram for the same.    (8Marks)

4. (a) Simplify the following using VEM technique. Reduce 4 variables to 3 variables

Y =rABCD -r ABC D + ABCD .    __

BCD -f AB CD + AB CD + ABCD + ABCD


Implement it using AOI logic.

(b)    Define fan-in and fan out -

(c)    Explain a two input NAND gate TTL with totem pole output with a neat circuit diagram.    (8 Marks)


(8 Marks) (4 Marks)


5. (a) Design 3:8 active low output decoder.

(b)    Compare Moore and Meelay models.

(c)    Construct 8:1 multiplexer using 2:1 multiplexer


(7 Marks) (8 Marks) (5 Marks)


Implement the following multi Boolean function using 3x4x2 PLA PLD

/i(a2>ai7ao) ~ (M,3,5) and /2(a2,a i,a-o)= m(3,5,7)

State Shannons expansion theorem and using this dieorem expand the following expression


6. (a)


(8 Marks)


(b)


(4 Marks)


/ = b~aC


Co


v*-.1



Page No... 2


9

?

4 synchronous down counter using JK flip flops and implement

(c) Design a MOD it.


. .    (S Marks)

*    p

7. (a) Define and explain, prime implicate.-

(5 Marks)


(b) Solve the following expression .using Boolean algebra technique

F = AB -f A(A + Cy+ A@Bl'0,. J-

(5 Marks


i v l


(c) Derive transition table. Statevtable and state diaer shown in below figure.

am for moore sequential circuit

(10 Marks)



t

** \

M * * *

*

- >

6*

i

1 * 4

x

r

._V

f.. I i!!j

* 1 4




#


i:


t,


I


rv


\


r r


* *


* /


8.


(a)    Explain the working of a CMOS, NOT, NAND and NOR gates.

V*    *    \    1 -    -; ; i '    - * l

(b)    Implement the following* multi-Boolean function using PROM PLD

/i(ii,x0) = xT + xn

/2(*l.*o) = ?l . ..

(c)    /(a,6,c,</) =771(1,2,3,5,6,7,11,12,13,14,15) for tlie above expression .i',.,i.r

. i) Draw the logic diagram using AOI logic for minimal sum. Obtain minimal sum using K-map.

ii) Find all the prime implicants and essential prime implicants.    (8 Marks)

a    b.    


(8 Marks)


(4 Marks)


*


** * **


V







Attachment:

( 0 Votes )

Add comment


Security code
Refresh

Earning:   Approval pending.
You are here: PAPER Visvesvaraya Technological University (VTU) 2005 B.E Electrical and Electronics Engineering 3rd Y/UST LOGIC DESIGN - Question Paper