Visvesvaraya Technological University (VTU) 2007 B.E Computer Science Eighth Semester , 08/ 09-Advanced Computer Architecture - Question Paper

Eighth Semester B.E.Degree Examination, Dec 08/ Jan 09
Advanced Computer Architecture
Time : three hrs Max Marks: 100
Note:Answer any 5 full ques..

1 With generic diagram, explain the architecture and operation of the following:
i) Shared memory multiprocessor systems.
ii) MIMD systems.
iii) Vector suprecomputers. (20 marks)

2 a. Consoider the subsequent sequence of instruction:
MOV R1,R2 ;R1 goes to R2
ADD R3,R2 ;(R3+R2) goes to R2
ADD R3,R4 ;(R3+R4) goes to R4
STORE R4,M2 ;R4 goes to memory at M4
STORE R2,M1 ;R2 goes to memory at M1
MOV R6,R4 ;R6 goes to R4
The processor executing these instructions takes 2 instructions of the provided
Sequence at a time and executes them simultaneously subject to data and resource dependences. In case it is not possible to execute both, it executes the 1st of the 2 instructions and tries to execute the 2nd instruction in the next time slot with the next instrcuction in the sequencce of instructions. Instructions are thus taken 2 at a time and executes simultaneously if possible. Consider every instruction takes 2 clock cycles.
How many clock cycles would the processor need to execute all the 6 instructions as provided above?
By changing the sequence of instruction can you improve the performance? What is the best sequence and what is the corresponding clock period for the above progarm segment of 6 instructions. (10 marks)
b. Compare the control and data flow architecture. Which architecture would expose parallelism to greater extent? (10 marks)

3 a. Consider a 10-dimensional hypercube interconnecting network.
i) How many process or nodes can it support?
ii) how many links does it have?
iii) Assuming the data travels by the shortest path, work out the number of links a
data has to pass to move from any node to farthest node.
iv) Indicate a minimum link path to reach from node 2D3 hex to node 2e5 hex.
(10 marks)
b.Indicate different causes for stalling in the instruction pipelines. provide a few idea about
reducing such stalling. (10 marks)

4 a. In respect of back plane buses. explain any 2 methods used for bus arbitration by
bus masters. (10 marks)
b. For the provided non-linear pipe line with the resevation table below, obtain the minimum
avg. latency cycle. If delay can be added, state what can be the maximum
throughtput possible from the pipe line? (10 marks)
Reservation table for the pipeline.
0 one two three four 5
S1 X X
S2 X X
S3 X X



5 a. In connection with instruction pipe line discuss with adequate details the following:
i) Dynamic instruction scheduling.
ii) Branch handling techniques. (12 marks)
b. define a pipilined floating point adder unit. (8 marks)

6 a. With a diagram discuss the operation of a 8x8 baseline network using ZxZ switch
Units. (10 marks)
b. Expalin the MESI protocol for maintaining cache coherence in a multiprocessor
system with every processor having its own cache. (10 marks)

7 a. Expalin how would you arrange the solutions of the simultaneous linear formula
AX=B with n unknowns, using a shared memory multiprocessor system with n/4
Processors. (10 marks)
b. Expalin the various steps like decomposition assignment etc. tp exploit parallelism
of a issue for execution by a set of parallel processors (10 marks)

8 a. Consider a single processor is able to solve a set of simultaneous linear equations in
1000 variables in 1 minute, and has just enough memory for this operation, using a
Process with a time complexity proportional to the cube of the number of variables.
compute assuming ideal conditions:
i) What size o issue can be handled by 900 such processors working in
Parallel and taking 1 minute for execution?
ii) What would be the memory constrained size of the problem?
iii) How much time would the issue of (ii) above take? (10 marks)
b. Write short notes on:
i) Parallelizing the ray tracing issue.
ii) VLIW architecture (10 marks)

Earning:   Approval pending.