Rajiv Gandhi Proudyogiki Vishwavidyalaya 2007 B.E Electronics and Instrumentation Engineering VLSI - Question Paper

VLSI (EI-8401)

Note: Attempt 5 ques. in all including no. one which is compulsory. Make suitable assumptions wherever necessary. Support your answers with suitable sketches.

1. (a) provide in short the answers of the following:

(i) What is Moore's law? [Marks 3]
(ii) describe sheet resistance. [Marks 3]
(iii) describe Interstitial Diffusion. [Marks 2]
(iv) What should be the value of the ratio Zp.u /Zp.d for an NMOS invertor driven through 1 or more pass transistors. [Marks 2]
(v) Why is the packing density of MOS transistors more than that of bipplar transistors ?
[Marks 3]
(vi) Write the advantages of ion implantation process over diffusion process. [Marks 4]

2. describe the subsequent phenomena associated with MOS transistors: [Marks 20]

(i) Body effect
(ii) Mobility variation
(iii) Impact ionization
(iv) Channel length modulation

3. (a) define the process of fabrication of silicn gate NMOS transistor. Clearly illustrate the sequence of processes with proper diagram. [Marks 12]

(b) Draw the cross-section of a CMOS transistor showing the parasitic transistor and resistors resulting in latch-up issue. Briefly discuss the reason of latch-up. [Marks 8]

4. (a) Draw the circuit diagram and stick diagram of the following: [Marks 10]

(i) 2 input CMOS NOR gate
(ii) 3 input NMOS NAND gate

(b) Draw the structure of a Twin Tub CMOS transistor. Write the relative merits of twin tub process over its other counterparts. [Marks 10]

5. (a) What do you mean by dynamic CMOS logic? Differentiate it from Domino CMOS logic. [Marks 10]
(b) discuss parity generator circuit with the help of structured design approach. [Marks 10]

6. (a) Illustrate the implementation of ALU functions with adders. [Marks 10]
(b) discuss in brief, a 4-bit serial parallel multiplier. [Marks 10]

7. (a) Draw and discuss the NMOS invertor circuit with its characteristics. Make use of a depletion mode transistor as the load. [Marks 10]
(b) discuss resistance estimation and capacitance estimation n brief. [Marks 10]

8. Write short notes on any 3 of the following: [Marks 20]

(i) Czochralski process (CZ process)
(ii) Mead conway design rules
(iii) Dynamic shift registers
(iv) replaced Booth's algorithm
(v) Small signal A.C characteristics of MOS transistors.

Earning:   Approval pending.