Rajiv Gandhi Proudyogiki Vishwavidyalaya 2010 B.E Computer Science and Engineering cso cs-401 s - Question Paper

RAJIV GANDHI PRODHYOGIK VISHWAVIDHYLAYA, BHOPAL
Computer System Organization
BRAANCH :CS
Duration: three hours
SEM – IV Max. Marks: 100

NOTE: Attempt any 5 ques.. every ques. carries equal marks
Q.1 (a)How many 128*8 RAM chips are needed to give a memory capacity of 2048 bytes?
(b)How many lines of the address bus must be used to access 2048 bytes of memory ?
(c)How many lines must be decoded for chip select? Specify the size of the Decoders.
Q.2 (a) discuss Register transfer language? Design a 5*32 decoder using 3*8 and 2*4 decoder?
b) Design the logic diagram of:
x : R1 ? R1 + R2
Q.3 (a) discuss DMA.
(b)Explain in brief about RAM, ROM, Bootstrap Loader, Cache Memory, Hit Ratio and kinds of mapping
Q.4 (a)What are various kind of addressing modes with example.
(b)Write 5 differences of Hardwired and micro programmed control
Q.5 (a)Draw the flow chart for Multiplication & its working with Booth.
(b) A two-way set associative cache memory uses blocks of 4 words. The cache can accommodate a total of 2048 words from main memory. The main memory size is 128K*32 . All info needed to construct cache memory.(tag and index etc.)
OR
Show the step by step multiplication process using Booth algorithm, when the binary number (+15)*(+13) using five bit register .
Q.6 Write Short Notes on the following: Any two:--
1. Direct Mapping
2. Page replacement algorithm
3. Virtual Memory
OR
What is daisy-chaining priority?

Earning:   Approval pending.