Pondicherry University 2007 B.Tech Electronics and Communications Engineering Very Large Scale Integrated Circuits (VLSI) - Question Paper

Year: November 2007
Semester: 5th semester
Subject: Very Large Scale Integrated Circuits (VLSI)
Paper Code: ET 3O3 R
Department: Electronics and Communication Engineering
Duration: three Hours Marks: 75

ans any 5 ques. by choosing 1 full from every unit

All ques. carry equal Marks

Unit I

1) Explain steps involved in the fabrication of CMOS using n- well process. (15)

(Or)

2) (a) Compare features of N MOS, C MOS, Bi CMOS (7)
(b) discuss the fabrication of inverter using twin tub process (8)

Unit II

3) Explain the principle of stick diagram and layouts diagram of MOS circuit design. (15)

(Or)

4) (a) What is scaling? Write its need. (6)
(b) discuss scaling factors for device parameters and brief scale models. (9)

Unit III

5) (a) discuss how transmission gate acts as EX-OR gate. (8)
(b) Implement PLA to perform squaring of 3-bit binary member. (7)

(Or)

6) Explain design of ALU in digital circuits and systems. (15)

Unit IV

7) Explain the steps involved in GaAs fabrication. (15)

(Or)

8) Brief FPGA economics, programmable logic cells GaAs crystal structure. (15)

Unit V

9) Model three X eight decoder using VHDL. Write a test bench for it. (15)

(Or)

10) Write a VHDL program for 4 bit counter and discuss. (15)

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All the best for examinations
Have a nice day and Love peace all time
With regards
Raaghavan Krishnamurthy

Earning:   Approval pending.