Jawaharlal Nehru Technological University Anantapur 2010-1st Sem B.Tech Code :R7411001 4 IV (R07) Regular s, ember/ember VLSI DESIGN - Question Paper

Code :R7411001 4
IV B.Tech I semester (R07) Regular Examinations, November/December 2010
VLSI DESIGN
(Electronics & Instrumentation Engineering, Electronics & Computer Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
1. (a) discuss step by step procedure for a typical n well process with neat diagrams.
(b) discuss the concepts of \Lithography" and probe testing related to IC production process.
2. (a) Draw and discuss their signi¯cance of different pull up forms.
(b) discuss the design considerations of Bi-CMOS inverter with suitable circuit diagram.
3. (a) Tabulate the encoding scheme for a simple single metal nMOS process with respect to
different MOS layers.
(b) Draw the symbolic layout for the CMOS inverter and provide the general CMOS logic gate
layout guidelines.
4. (a) What is meant by standard unit of capacitance? provide a few area capacitance computations.
(b) discuss the concepts of `nMOS inverter pair delay' and `Minimum size CMOS inverter
pair delay' with necessary circuit diagrams.
5. (a) elaborate Wallace tree elements? provide and discuss in example of the Wallace tree ap-
proach.
(b) Draw a 4 bit braun multiplier and provide its subsystem level design considerations.
6. (a) Di®erentiate PAL and PAL with respect to different performance parameters.
(b) Write notes on complex programmable logic devices.
7. (a) Draw the block diagram of synthesis process and illustrate with an example.
(b) define the VHDL synthesis approach with an example.
8. (a) discuss the CMOS testing principles.
(b) elaborate the system level test techniques? discuss 1 of them with an example.

Earning:   Approval pending.