Jawaharlal Nehru Technological University Anantapur 2010-1st Sem B.Tech Code :R7411001 3 IV (R07) Regular s, ember/ember VLSI DESIGN - Question Paper

Code :R7411001 3
IV B.Tech I semester (R07) Regular Examinations, November/December 2010
VLSI DESIGN
(Electronics & Instrumentation Engineering, Electronics & Computer Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
1. (a) discuss the nMOS fabrication process with suitable diagrams.
(b) discuss the IC production process concept of "Oxidation" and "Ion implantation'.
2. (a) De¯ne the subsequent with necessary expressions.
i. gm
ii. gds
iii. Figure of Merit
(b) obtain the pull-up to pull-down ratio for an nMOS inverter driven through 1 or more pass
transistors.
3. (a) discuss in detail about \VLSI design °ow" with neat °ow diagram.
(b) elaborate limitations of scaling for VLSI circuits and brie°y discuss them.
4. (a) What is meant by sheet resistance Rs? discuss the concept of Rs applied to MOS tran-
sistors.
(b) discuss in detail about formal estimation of CMOS inverter delay.
5. (a) provide the subsystem design considerations of a four-bit adder.
(b) discuss step by step subsystem design approach. Consider adder as an example.
6. (a) Illustrate how logic functions can be realized using nMOS PLA with an example.
(b) discuss the design °ow of standard cell with neat diagram.
7. (a) discuss any 1 of the design capture tools available for VHDL synthesis with an example.
(b) elaborate the different VHDL veri¯cation tools? discuss any 1 of item.
8. (a) define the design strategies for CMOS testing.
(b) explain about layout design for improved testability. Consider a suitable example.

Earning:   Approval pending.