Jawaharlal Nehru Technological University Anantapur 2010-1st Sem B.Tech Code :R7411001 2 IV (R07) Regular s, ember/ember VLSI DESIGN - Question Paper

Code :R7411001 2
IV B.Tech I semester (R07) Regular Examinations, November/December 2010
VLSI DESIGN
(Electronics & Instrumentation Engineering, Electronics & Computer Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
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1. (a) Tabulate the comparison ranging from CMOS and Bipolar Technologies.
(b) define the terms \Metallization" and \Encapsulation" relevant to IC fabrication process.
2. (a) Draw and discuss the characteristics of nMOS transistor in di®erent modes of operation
and its body e®ect.
(b) provide the design aspects and draw the circuit diagram of nMOS inverter and with the help
of transfer characteristics.
3. (a) discuss with suitable diagrams, the lambda-based design rules.
(b) De¯ne and provide the expressions for any 4 scaling factors of MOS device parameters.
4. (a) explain about area capacitances of MOS layers and provide area capacitance computations with
suitable examples.
(b) Illustrate driving large capacitive loads with relevant examples.
5. (a) define the nature of a parity generator and discuss its structured design approach.
(b) Draw and provide the design approach for a carry look ahead adder with its structure.
6. (a) discuss semiconductor integrated circuit design approach using programmable logic ar-
rays.
(b) Compare the performance parameters of Complex programmable logic devices and ¯eld
programmable gate arrays.
7. (a) discuss the subsequent with respect to VHDL synthesis.
i. Simulation
ii. Layout.
(b) List the different VHDL veri¯cation tools and discuss any 1 of them.
8. (a) define the different design strategies used for CMOS testing.
(b) Write notes on system-level CMOS testing techniques.

Earning:   Approval pending.