Jawaharlal Nehru Technological University Anantapur 2010-1st Sem B.Tech Code :R7411001 1 IV (R07) Regular s, ember/ember VLSI DESIGN - Question Paper

Code :R7411001 1
IV B.Tech I semester (R07) Regular Examinations, November/December 2010
VLSI DESIGN
(Electronics & Instrumentation Engineering, Electronics & Computer Engineering)
Time: three hours Max Marks: 80
ans any 5 ques.
All ques. carry equal marks
1. (a) provide the comparison ranging from CMOS and Bipolar technologies.
(b) discuss the processing steps used in IC fabrication process.
2. (a) Deduce the expressions for drain-to-source current verses drain to source voltage relations.
(b) explain on MOS transistor threshold voltage.
3. (a) discuss step by step procedure for drawing stick diagram for single metal single polysilic-
con nMOS technology.
(b) current the general CMOS logic gate layout guidelines and draw the used de¯ned layout
drawing conventions.
4. (a) Draw and discuss fan in and fan out characteristics of di®erent CMOS design technologies.
(b) elaborate the alternate gate circuits available? discuss any 1 of item with suitable
sketch.
5. (a) what are the concept of pipelining relevant to subsystem design principles.
(b) Draw and discuss the architecture of a high-density memory system.
6. (a) Draw the general architecture of programmable logic array and discuss.
(b) explain about Field programmable gate arrays.
7. (a) discuss the VLSI circuit design °ow with neat °ow diagram.
(b) With suitable block diagrams, discuss the terms \Hardware simulation" and \Synthesis
Process".
8. (a) What is meant by CMOS testing? discuss the need for testing.
(b) discuss the concept of layout design for improved testability with suitable examples.

Earning:   Approval pending.