Guru Gobind Singh Indraprastha Vishwavidyalaya 2006-6th Sem B.Tech [] - , Code : ETEC – 310 Subject : VLSI Design - Question Paper

Second-Term exam
6th Semester [B.Tech] - April 2006

Paper Code : ETEC – 310 Subject : VLSI Design

Time : 11/2 Hours
Maximum Marks : 30

Note : Attempt any three ques. in all. Q1 is compulsory. every ques. carries 10 marks.


Q1
( a )
Compare the features of NMOS depletion-load logic gates and CMOS logic-gates.


( b )
Compare the features of TG and NMOS pass devices.
( c ) explain the parasitic capacitances SR-CMOS and the trise
( d ) Charge storage and charge leakage with respect to NMOS pass transistors.
( e ) explain DRAM operation modes.


Q2
( a )
For a CMOS NOR2 gate, prove that if kn=kp and VT,n=|VT,p| then



( b )
Implement F = (A.B + C.D)' in CMOS.



Q3
( a )
For the CMOS SR flip-flop, shown in figure 3, the 4 transistors M5, M6, M7 and M8 have equal W/L ratios. Determine the minimum value needed for this ratio to ensure that the flip-flop will switch. The other relevant parameters areas follows:
u,=2.5 upCOX=50uA/V2 VT,n=|VT,p|=1V
For M1 and M2 (W/L)n = 4u / 2u and for M3 and M4 (W/L)p = 10u / 2u







Q5

Write short notes on any two:

( a )
Precharge and evaluate switch of Dynamic logic.

( b )
discuss with a neat diagram the clocked D-latch employing TG and CMOS.

( c )
With a neat timing diagram define the operation of a 3-transistor DRAM cell.

Earning:   Approval pending.