Guru Gobind Singh Indraprastha Vishwavidyalaya 2006-6th Sem B.Tech [] - , Code : ETEC – 310 Subject : VLSI Design - Question Paper

First-Term exam
6th Semester [B.Tech] - February 2006

Paper Code : ETEC – 310 Subject : VLSI Design

Time : 11/2 Hours
Maximum Marks : 30

Note : Attempt any three ques. in all. Q1 is compulsory. every ques. carries 10 marks.


Q1
( a )
With a neat flow diagram explain the VLSI design methodology.


( b )
define in brief about regularity, modularity and locality.
( c ) Advantages and disadvantages of standard-cells based design.
( d ) Noise margin in MOSFET inverter.
( e ) Draw a neat diagram (isometric/oblique view) of an N-channel enhancement kind MOSFET.


Q2
( a )
explain in brief about:

Photolithography
Metallization and Polysilicon
Device isolation techniques
CMOS n-well process.




Q3
( a )
Write in brief about:
legal regulations of mass action
Equilibrium Fermi level
Surface inversion
Threshold voltage
Channel length modulation


( b )
Derive the subsequent relationship of an N-channel MOSFET:


(Where the notations have their usual meaning.)



Q4
( a )
explain in detail the CMOS inverter with a resistive load and critical factors that affect the layout design.





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