Guru Gobind Singh Indraprastha Vishwavidyalaya 2005 B.Tech Digital Circuit and Systems I - Question Paper

First-Term exam
Fifth Semester [B.Tech] - September 2005

Paper Code : ETEC – 301 Subject : First-Term exam
Fifth Semester [B.Tech] - September 2005

Paper Code : ETEC – 301 Subject : Digital Circuit and Systems I

Time : 11/2 Hours
Maximum Marks : 30

Note : Attempt any three ques. in all. Q1 is compulsory. every ques. carries 10 marks.


Q1
( a )
How are hazards avoided using SR latches.
2

( b )
Distinguish ranging from Mealy model and Moore model. one
( c ) A sequential circuit has 2 JK flip flops A and B, on input y, and 1 output y. The J and K inputs are described as:
Ja = B, Kz = B', Jb = Kb = (xA' + x'A)'
y = ((x'A + xA')B' + (xA' + x'A)'B)

Derive the state table.
three
( d ) elaborate cycles in asynchronous circuits. provide examples. two
( e ) Assign output values to the dont care conditions in the subsequent flow tale: 00 01 11 10
A D,- A,0 A,0 B,-
B B,1 B,1 C,- B,1
C B,- C,1 C,1 D,-
D D,0 D,0 A,- D,0
two


Q2
( a )
A sequential network has 1 input (X) and 1 output (Z). The network examines groups of 4 consecutive inputs and produces an output Z=1 if the input sequence 0101 or 1001 occurs. The network resets after every 4 inputs. Determine the mealy state graph and state table.
6

( b )
Draw an ASM chart that specifies a conditional operator to increment register R during state T1 and transfer to state T2 if control inputs z and y are equal to one and 0 respectively.
four


Q3
( a )
Determine the state table corresponding to the subsequent state diagram:

3

( b )
Design an asynchronous sequential circuit with 2 inputs x1 and x2 and 1 output z. initially both inputs and outputs are equal to 0. When x1 or x2 becomes 1, z becomes 1. When the 2nd input also becomes 1, the output becomes 0. The output stays at 0 until the circuit foes back to the initial state.
find the primitive flow table and show that it can be decreased to the subsequent flow table:
00 01 11 10
A A,0 A,1 B,- A,1
B A,- B,0 B,0 B,0

Design the circuit using SR latches.



Q4
( a )
USE IMPLICATION TABLE TO decrease THE subsequent TABLE TO A MINIMUM NUMBER OF STATES:
current STATE NEXT STATE OUTPUT
X=0 X=1 Z
A F D 0
B D A one
C H B 0
D B C one
E G B 0
F A H 0
G E C 0
H C F 0
3

( b )
The state diagram of a control unit is as shown beneath. It has 4 states and 2 inputs x and y.


Draw the equivalent ASM chart
Design the control unit using D flip flops and decoders.



Time : 11/2 Hours
Maximum Marks : 30

Note : Attempt any three ques. in all. Q1 is compulsory. every ques. carries 10 marks.


Q1 ( a ) How are hazards avoided using SR latches.


( b ) Distinguish ranging from Mealy model and Moore model. one
( c ) A sequential circuit has 2 JK flip flops A and B, on input y, and 1 output y. The J and K inputs are described as:
Ja = B, Kz = B', Jb = Kb = (xA' + x'A)'
y = ((x'A + xA')B' + (xA' + x'A)'B)

Derive the state table.

( d ) elaborate cycles in asynchronous circuits. provide examples. two
( e ) Assign output values to the dont care conditions in the subsequent flow tale: 00 01 11 10
A D,- A,0 A,0 B,-
B B,1 B,1 C,- B,1
C B,- C,1 C,1 D,-
D D,0 D,0 A,- D,0


Q2 ( a ) A sequential network has 1 input (X) and 1 output (Z). The network examines groups of 4 consecutive inputs and produces an output Z=1 if the input sequence 0101 or 1001 occurs. The network resets after every 4 inputs. Determine the mealy state graph and state table.


( b ) Draw an ASM chart that specifies a conditional operator to increment register R during state T1 and transfer to state T2 if control inputs z and y are equal to one and 0 respectively.

Q3 ( a ) Determine the state table corresponding to the subsequent state diagram:

( b ) Design an asynchronous sequential circuit with 2 inputs x1 and x2 and 1 output z. initially both inputs and outputs are equal to 0. When x1 or x2 becomes 1, z becomes 1. When the 2nd input also becomes 1, the output becomes 0. The output stays at 0 until the circuit foes back to the initial state.
find the primitive flow table and show that it can be decreased to the subsequent flow table:
00 01 11 10
A A,0 A,1 B,- A,1
B A,- B,0 B,0 B,0

Design the circuit using SR latches.


Q4 ( a ) USE IMPLICATION TABLE TO decrease THE subsequent TABLE TO A MINIMUM NUMBER OF STATES:
current STATE NEXT STATE OUTPUT
X=0 X=1 Z
A F D 0
B D A one
C H B 0
D B C one
E G B 0
F A H 0
G E C 0
H C F 0

( b ) The state diagram of a control unit is as shown beneath. It has 4 states and 2 inputs x and y.


Draw the equivalent ASM chart
Design the control unit using D flip flops and decoders.

Earning:   Approval pending.