Guru Gobind Singh Indraprastha Vishwavidyalaya 2008-2nd Year B.C.A Computer Application Computer Architecture, Third Semester, End Term , Year , , - Question Paper
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Q1 (a) What (* wrong w4h the following register transfer statements? (5) (I) *r :/<*-33?, AR+-0 (K) yT: ftl *- *2, tfl *- Ri
i/te) Eipttin the indexed addressing mode. (5) v. (d) V/mt the difference between oiated I/O and memory mapped I/O? Also, explan
fca advantages end dadvantages of each. (6)
Jj) 'Mm <e memory hierarchy in a computer system? (5)
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02 Irf Starts from an anKM value of R-11011101. determine the sequence of tinery
values in R after a logical eMt-left. folowed by e circular shift-right folowed by a logical aMt-right and a circular sNft-left. (4.6)
<tfr Design an anthmeoc circuit w*h one selection variable S and two n*Wt date inputs A and 8. The circuit generate* the following four arithmetic operation in conjunction wll f>e mom carry C. Draw the logic diagram tor the first two stages (8)
S ClnsQ " ~ Cr>1 ~
( 0 D*A*8 0A*1_
I 1 0*A-1_DA B +\_1
03 (a) VWiat is the dfferenoe between a direct and an indirect address instruction? How
many references to memory are needed for each type of instruction to bring an operand Wo a proceesor register? (45)
(b> Draw the block diagram of controfepnft of basic computer and explain. (8)
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QV (a) Draw full adder and explain to logic circuit. (46)
' (b) VWiel are the various phases of an insfructton cycle? Give the microoperanons of fetch and decode phases. How the first two register transfer statements are implemented? I*)
OS (a) What is the reverse polish notation? Eiq>iain with an example (4.8)
(b) VWto down a program to evaluate Z ~ {A + 8)*(C* D)*{G + using tnree address instructions and zero addrea* instruction* (8)
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08/ (e) What do you understand by the divide overflow? (4)
'(b) Show the contents of revelers E, A, Q and SC during the process of multiplication of two binary numbers. 11111 (nxrtiplicend) and 10101 (muflptter). The *gns ere not Included (8 5)
07 (a) Draw a Mock diagram for the DMA system ehomng the eesential efemerrts needed
for the DMA transfer in a computer system. (4J)
(b) Explain the tffferenoe between the daisy chaining priority and paralel priority interrupts. Oraw the degrams to explain their working (8)
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08 / (a) Explain the concept of virtual memory What are its advantages? (4.6) ,/ (b) What Is associative memory? Gfve and explain its architecture (8)
09 (a) Explain the dtfferenoes between cache and suxftary memory. (4.8)
(b) A two-way set associative cache memory usee blocks of four words. The cache can
accommodate a total of 2048 words from main memory The mein memory size is128Kx32. (8)
(i) Formulate aK pertinent information required to construct the cache memory.
(ii> What ia the size of the cache memory?
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