Cochin University of Science and Techology (CUST) 2008-2nd Year B.Tech Electronics and Communications Engineering LOGIC DESIGN - Question Paper

2nd TERM exam MARCH 2008

LOGIC DESIGN

Max marks 50



1. Show the multiplication of binary 10101 by 11010

2. discuss what is mean by PAL and PLA

3. Briefly discuss the various logic families

4. Implement a half adder using NAND only

5. discuss briefly astable multivibrator

6. a) Simplify the subsequent formula using K-map
V=f(a,b,c,d)= m(2,3,4,5,13,15) + d (8,9,10,11)

b) Draw the logic symbol and truth table of a half subtractor

OR

7. a) Draw a neat diagram and discuss a carry look ahead adder.

b) discuss the block diagram of a parallel binary multiplier.

8. a) discuss 2 input TTL NAND gate.

b) Compare totem pole and open collector.

OR

9. a) discuss interfacing of TTL to CMOS & CMOS to TTL .

b) discuss ECL NOR/OR gate.

c) discuss subsequent terms

1. Noise margin

2. FAN OUT

3. FAN IN
4. Propagation delay.

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Earning:   Approval pending.