Cochin University of Science and Techology (CUST) 2007 B.Tech Electronics and Communications Engineering VLSI Design (e ) - Question Paper

VLSI Design(June 2007)

1a. discuss the twin-tub process for CMOS fabrication with neat sketches
b. Compare the performance of CMOS and Bipolar technology
2a. discuss about ion implantation in IC fabrication with necessary diagrams
b. Compare the material properties of Ga As and Si
3a. discuss about the energy distribution of a nMOS structure under
i) accumulation ii) depletion iii) inversion
b. Derive an expression for drain current in a long channel MOSFET and discuss the different modes of operation under various voltages
4a. Determine the pull up to pull down ratio of an nMOS inverter driven by a different nMOS inverter
b. Derive the expression for the trans conductance of an nMOS transistor in terms of transistor parameters
5a. define the realization of the subsequent CMOS logic gate
i)2 input NAND gate ii)2 input NOR gate
b. discuss about the issues associated with driving large capacitance loads by CMOS inverter? How these issues can be remedied?
6a. Draw the stick diagram of CMOS inverter and discuss
b. Draw the CMOS inverter DC transfer characteristics and discuss different regions of operation
7a. discuss different implementation strategies of digital IC's
b. discuss clocked CMOS(c2MOS) with neat diagram
8a. discuss with diagrams the 3 classes of bus lines
b. Draw the stick diagram of nMOS parity generator and discuss its working
9a. discuss the timing classifications of digital systems
b. discuss about self timed circuit design
10a.Explain about the combined impact of skew and jitter in the performance of a sequential system
b. Compare synchronous and asynchronus systems

Earning:   Approval pending.