Cochin University of Science and Techology (CUST) 2006 B.Tech Electronics and Communications Engineering VLSI DESIGN - Question Paper
B.Tech. Degree VII Semester Examination, November 2006
(2002 Admissions onwards )
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Hours |
Maximum Marks: 100 | |
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a) |
Draw and explain the process of n-wcll CMOS fabrication. |
(8) |
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b) |
Discuss the flow diagram of n-well technology. |
(6) |
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c) |
Compare between monolithic and hybrid ICs and also mention about its | |
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application areas? |
(6) | |
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OR | ||
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a) |
Explain why GaAs is preferred than Si in microwave monolithic ICs. |
(5) |
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b) |
Compare the material properties of GaAs and Si. |
(5) |
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c) |
Discuss about the high current and high energy ion implantation equipment and | |
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explain how it varies from a typical ion implantcr with relevant diagram. |
(10) | |
a) Derive an expression for drain current for long channel MOSFET and explain the
various modes of operation under different voltages. (I 0)
b) Discuss about various second order effects in MOSFETS. (10)
OR
a) Derive an expression for pufl up to pull down ratio for an NMOS inverter driven
by another NMOS inverter. (J 0)
b) A PMOS structure has a substrate doping of N=1010cm'} and a gate doping of Nfl-lOcm*3. The oxide charge density is Qcl-4 x 10' q=6.4nC/cm2 and thickness is tulOOO angstroms.
Calculate the threshold voltage with zero substrate bias
Calculate the body coefficient y (10)
Discuss the need of design rules? What is the difference between X rules and micron rules. Draw the circuit diagram: stick diagram and layout of a two input CMOS NAND gate? (20)
OR
a) Discuss the need of super buffers and explain the woiking of inverting and non-inverting super buffers. (10)
b) Explain the concept of sheet resistance and MOS dcvice capacitance with relevant Equations. (10)
a) Discuss the various implementation strategies of digital ICs. (10)
b) Explain the working of clocked CMOS (CrMOS) logic with diagram. (10)
OR
a) Explain the working of a two input XNOR gage using pass transistors. (5)
b) Implement the function Z=<A.B)+(C.D) using CMOS logic and draw its stick diagram. (15)
a) What is clock skew and discuss the cffect of positive and negative clock skew on
clock period with relevant diagrams and equations? (10)
b) Explain the concept and implementtion of synchronizers. (10)
OR
Write short notes on:
(i) Synchronous versus asynchronous
(ii) Self timed circuit design
(iii) Clock distribution techniques (20)
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Attachment: |
| Earning: Approval pending. |
