Cochin University of Science and Techology (CUST) 2011-5th Sem B.Tech Electrical and Electronics Engineering BTech Iester ,il - EE 404 COMPUTER ARCHITECTURE AND ORGANISATION ( 2002 scheme) - Questio

BTS (C) - IV - 11 - 020 -1

B.Tech Degree IV Semester Examination April 2011

EE/EI 404 COMPUTER ARCHITECTURE AND ORGANISATION

(2002 Scheme)

Time : 3 Hours    Maximum Marks : 100

I.    (a) Explain the different addressing modes.    (10)

(b) Explain micro programmed control in detail. (10)

OR

II.    (a) Explain the design of fast adders.    (10)

(b) Explain Non-restoring division algorithm with example. (10)

III.    (a) Explain virtual memory and address translation in detail.    (10)

(b) Write notes on :

(i)    SRAM

(ii)    Bipolar and MOS devices

(iii)    DRAM    (10)

OR

IV.    (a) Explain Cache Memory in detail.    (10)

(b) Explain the different mapping functions. (10)

V.    (a) Explain about the following:

(i)    Daisy chaining

(ii)    Buses

(iii)    Plotters and VOVs    (15)

(b) Explain about interrupts. (5)

OR

VI.    (a) Explain about DMA in detail.    (10)

(b) Explain about interrupt nesting. (10)

VII.    (a) Explain the interrupt structure of 8085.    (10)

(b) Explain in detail about the control signal functions. (10)

OR

VIII.    (a) Describe the architecture of 8085 with functional block diagram.    (15)

(b) What is the importance of status flags? (5)

IX.    (a) Explain the various addressing modes of 8085.    (10)

(b) Explain I/O mapped I/O and memory mapped I/O. (10)

OR

X.    (a) Explain the instruction set of 8085.    (10)

(b) Write an assembly language program to sort a series of numbers in ascending

order.    (10)

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Attachment: cochin-university-of-science-and-techology--cust--2011-b-tech-electrical-and-electronics-engineering-36973-1.pdf

Earning:   Approval pending.