Rajasthan Technical University 2010 B.Tech Computer Science and Engineering Vll Sem.(Main) ,- Computer Science LOGIC SYNTHESIS - Question Paper

B.Tech. Vll Sem.(Main/Back) Examination, December - 2010
Computer Science
7CS3 LOGIC SYNTHESIS
Time: three Hours Total Marks: 80
Min. Passing Marks: 24
Instructions to Candidates :
Attempt overall 5 ques. selecting any 1 ques. from every unit. All ques. carry equal marks. (Schematic diagrams must be shown whenever necessary. Any data you feel missing may suitably be presumed and said clearly. Units of volumes used/calculated must be said clearly.)

UNIT - I
Q.1.(a) discuss various micro electronic design styles. (6)
(b) discuss ROBDD with suitable example. (10)
OR
Q.1.(a) discuss the 4 phases in creating micro electronic chips. (8)
(b) discuss Moore's legal regulations. (3)
(c) discuss vertex cover and clique covering in graph. (5)

UNIT - II
Q.2.(a) discuss fundamentals architectural synthesis issues in hardware modelling. (6)
(b) discuss calculation and behavioural optimization techniques. (6)
(c) discuss circuit specifications for architectural synthesis in brief. (4)
OR
Q.2. Write short notes on the following(Any Four): (16)
(i) Data flow graph
(ii) Sequencing graph
(iii) State Diagram
(iv) Bipartite graph
(v) Logic network

UNIT - III
Q.3.(a) discuss the model for scheduling issues. (6)
(b) discuss ASAP and ALAP scheduling algoritms with examples. (10)
OR
Q.3.(a) discuss force directed scheduling with example. (8)
(b) discuss multiprocess scheduling. (8)

UNIT - IV
Q.4.(a) discuss algorithm for exact logic minimization. (8)
(b) discuss positional cube notation of binary valued function and multiple value functions. (8)
OR
Q.4.(a) What is heuristic logic minimization? discuss. (6)
(b) discuss the subsequent :
(i) Minimum cover (3)
(ii) Redundant cover (3)
(iii) PLA implementation of logic function (4)

UNIT - V
Q.5.(a) discuss State encoding in Two-level circuits. (8)
(b) discuss algorithm for sequential optimization. (8)
OR
Q.5.(a) discuss sequential circuit optimization using state based models. (10)
(b) discuss synchronous circuit optimization using network models. (6)

Earning:   Approval pending.