Rajasthan Technical University 2010-5th Sem B.Tech Computer Science and Engineering (Main) , / 2011 5CS2 Digital Logic Design - Question Paper

B.tech five Semester (Main) Examination, Dec. 2010/Jan. 2011
Computer Science
5CS2 Digital Logic Design


Unit-I

1.
A) discuss with example the lexical elements of VHDL language.
B) What is the modeling concept of VHDL? discuss.

OR

2. Explain the concept of look ahead carry adder in VHDL language.

Unit-II

3.
A) discuss the concurrent statements with suitable examples.
B) What is the use of VHDL in synthesis? discuss with a suitable example.

OR

4.
A) What do you understand by resolved signals? discuss.
B) discuss packages and use clauses of VHDL language.


Unit-III

5.
A) Is there any difference ranging from Moore and mealy machines? discuss.
B) discuss clock skew, set up time and hold time with suitable examples.

OR

6.
A) Is there any difference ranging from PAL and PLA? discuss with examples.
B) What is meant by FPGA? discuss briefly.


Unit-IV

7.
A) discuss the procedure of state reduction of incompletely specified machine with a suitable example.
B) discuss function hazards with suitable examples.

OR

8.
A) What do you understand by dynamic hazards? discuss with examples.
B) What is meant by race-free assignments?

Unit-V

9. What are the differences among SRAM, EAPROM and flash memory.

OR

10.
A) What is the importance of Altera Stratix?
B) Why should 1 prefer Xiliux Virtex-II pro.?

Earning:   Approval pending.