Rajasthan Technical University 2010-7th Sem B.Tech Computer Science and Engineering (Main) Computer science & engineering, Logic Sysnthesis - Question Paper
Rajasthan tech. University
B.Tech seven sem (Main)
Computer science & engineering,Jan 2010
(7CS3) Logic Sysnthesis
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B.Tsdi(Sam.Vfl) (Main) Examination, January 2010 Cowpimr Scianca (7CS3 Logie Syntttaaia)
Tima: 3 Hours) (Total Marks. 80
Attempt overall tfve questions selecting on* question [rom each unit.. All questions carry equi ,T.arks. (Schematic aag/ams ir.uk c s/ww wherever necessary Any data you feel miqsmg may suitably be assumed and stated dearly. Units of quantities used/calculated rust os stated cleariy}
Use of fcftovwing sufjporting material is periniftrd during exv.iinafion (Mentioned in form Wr. >'a>/
1._____Nil_________ 2.________*_____________
1 (a) Explain th? fouj j-hasos in creating nuoro tlwtronw't. c.nro> .a conipui r_:-).-.. d -synthesi-- and O'.tirViZtn,!:
(b) Explain t!>- algorithm review of smph <k :;nii*-.-ns r; notations.
6
OK
% Write short iicit'S t,a any tour :
6) Vertex covcr
(ii) Grapli coloring
(iii) Clique covering anil partitioning
(iv) Asjos and Moore's law
(v) Micro electronic Design.
16
7E4093J igffilimiUgi 1 * IContd...
UNIT - II
1 (a) GitpW th? compilation and bduvinual techniques. 6 (fci Explain the <arruita specifications tor architectural synthesis
resources ?nd constraints.
10
2 Wnte short novw on f*cy tamr :
6) Data flf>w and sequencing graphs (ii) Temporal .lomain scheduling ja) Htrd-urv modeling laaguage uv' Hu-rarrihira! models and synchronisation
(v) ;frfi.taiinc(> Eslniitioa Resource doaiiaated and general cirruitu
16
I (a) ixp:an -the scheduling: algorithm latency.
6
lb) 'vvil.f-n 'he vjriclor timing constraints and relative scheduling vitb i-sou;ce constraints integer linear programming model.
10
OR
i Write short notes ,-vi any four :
<i) Forcedirecied scheduling
(ii) Muitiprocsssor scheduling
(iii) Scheduling constraints and resources
(iv) ALAP ehedtrling
(Y> H"rist?e seiiduling algorithms.
16
i, (a) Expl*au i.he functions with multivounie inputs and list _ oriented iranipuiation.
10
(1)} VVhat ars combinational cirruits?
' 3
(c) What aru sequential circuits?
3
7E40931 1JSl !fH || HI tt9 HI 2 (Contd...
2 (a) Explain the exact logic minimization and principle for logic optinmatioa.
8
(b) Explain the testability properties operations on two level logic cover-positional cube notation.
8
1 (a) Explain the sequential circuit optimization using state based
model*.
Ii) Etplain the testability consideration for synchronoui amuK
6
2 (a) Explain the sequential circuit optimization using network
RWtels.
10
(b) Kxplain the implicit finite state machine traversal methods.
6
7E4093J IlHHIHII 3 | 4500 |
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