Rajasthan Technical University 2011-8th Sem B.Tech Computer Science and Engineering (Main) Computer science & engineering,/ch , CAD for VLSI - Question Paper
Rajasthan tech. University
B.Tech eight sem (Main)
Computer science & engineering,Feb/March 2011
(8CS2) CAD for VLSI
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Roll No. :
B. Tech. (Sem. VIII) (Main) Examination, February/March - 2011
Computer
8CS2 CAD for VLSI Design
8E4015
Total Printed Pages :
Time : 3 Hours] [Total Marks : 80 [Min. Passing Marks : 24
Attempt any five questions, selecting one question from each unit. All Questions carry equal marks. (Schematic diagrams must be shown wherever necessary. Any data you feel missing suitably be assumed and stated clearly. Units of quantities used / calculated must be stated clearly
Use of following supporting material is permitted during examination. (Mentioned in form No. 205)
1. Nil 2. Nil
1 (a) What is ASIC? Ilow ASIC is classified? State the advantages
and disadvantages of ASIC Design.
(b) Explain the steps of CAD flow for designing with ASIC.
OR
1 (a) What do you mean by productivity gap? Explain the
productivity gap in terms of time to market.
(b) Explain the steps of FPGA design flow. What is the difference between FPGA & ASIC?
6+2
(a) Discuss tlie requirements that led to the design of VHDL language.
10
(b) Which of these advantages that software language does not have and VHDL have?
OR
8E40I5]
[Contd...
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2 (a) Describe the elements of VHDL stating the examples.
(b) Show the waveform on x for following code Architecture sequential of discarding old is Signal x : bit : = z begin process begin
x <= 1 after 5 ns; x <- Transport O' after 3 ns;
wait
end process: end sequential;
6
3 (a) Write a VHDL description for RS latch. Use the fast single
delay model of nand-2 to avoid oscillation.
(b) State different types of VHDL operators.
8
3 Write the short note on :
(i) Binding Alternatives
8
(ii) Design Parameterization in VHDL.
4 Write short note on :
(i) Subprogram Parameter Types
8
8
(ii) Overloading in VHDL.
4 (a) Write short note on :
(i) P re-defined attribute
(ii) User-defined attribute
4
(b) Bi-directional component modelling
8E4015) | IIJ II11 HI ill I 2 [Contd...
State difference between behavioural style of modelling and dataflow style of modelling.
5 (a)
(b)
5 (a) (b)
Write a VHDL code for seven-segment decoder using dataflow style of modelling.
Write the VHDL code for D-flipflop using behavioural style of modelling.
Write the VHDL code for basic up-down counter using behavioural style modelling.
III!
III!
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8E4015]
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| Earning: Approval pending. |
