Rajasthan Technical University 2009-8th Sem B.E B.Tech (Main/Back) Advanced computer architecture - Question Paper
Rajasthan tech. University
B.Tech eight sem (Main/Back)
Advanced computer architecture
Paper II
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IV B.E. (VIII SEMESTER) (MAIN/BACK) EXAMINATION, 2009
(New Four Year Semester Scheme)
[Branch : Computer Engineering} 1 Paper II
ADVANCED COMPUTER ARCHITECTURE 0'
Time Allowed : Three Hours Maximum Marks 80
Turn ever
No supplementary answer-book will be given to any candidate. Hence the candidates should write the answer precisely in the Main answer-book only.
1. (a) Describe Flynns Fengs and Handlers
architectural classification of parallel computing scheme in brief. 8
(b) How is time sharing concept advantageous ovr multiprogramming? Explain with diagram. o
2. (a) What are the various trends towards parallel
processing?
(b) Discuss the latency and synchronization issues that limit the performance of parallel system. 4
(c) Describe in brief Array processor and multiprocessor system.. <S
3. (a) What are various pipeline hazards caused 'by
resource usage conflicts in various instructions. Also discuss the method to resolve them. 4+4
(,b) What do you mean by vector processing? Discuss the architecture of a typical vector processor vviI'f multiple functional pipe. 2 + 6
4. (a) Describe interleaved memory organization in
detail. ' - '8
(b) Explain the principle of linear pipelining; Derive formula for clock period, frequency, speed up and throughput. 4 + 4
5. (a) Draw and describe the architecture and working of s tatic data floW computers. 8
(b) How is control flow computei different from data flow computers? 8
(a) Discuss in J>rief the following SIMD interconnection networks:
(i) Mesh connected Illiac networks
(ii) Cube interconnection networks. 4+4
(6) Describe masking and data routingjjiechanism in SIMD Array processor. 8
7. (a) Describe internal forwarding and register tagging.
8
(b) Following is a reservation table for a unifuncncn pipeline:--
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 | |
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i. |
X |
X | |||||||
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2 |
X |
X |
X | ||||||
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3 |
X | ||||||||
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4 |
X |
X | |||||||
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5 |
X |
X |
Answer, the following questions:
(/) List the set of forbidden latencies between task irriiation. Also show the collision vector.
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(ii) Draw the state diagram that shows all the possible latency cycles.
(iii) List all the simple cycles from state diagram.
(iv) List all greedy cycles from state diagram.
(v) What is the value of the MAL and maximum throughput of above shown pipeline.
2+2 +1+1+2=8
8. Explain (any four):
(/) Serial versus Parallel processing
(ii) Data Buffering in pipelined processor
(iii) Inter PE communication.
(/V). Systolic Arrays
(v) Vector processing requirement. 4x4=16
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Attachment: |
| Earning: Approval pending. |
