Biju Patnaik University of Technology 2008 B.Tech Electronics and Tele-Communication Engineering VLSI Design - Question Paper

1. (i) choose the accurate answers for the subsequent
ques. from the option provided : (1×6)

(a) Feature size in MOS technology
refers to half of the channel length
of the smallest transistors and is
denoted by the symbol

(i) delta a adf
(ii) beta abf
(iii) lambda alf
(iv) epsilon aef

(b) Threshold voltage VT is described as
the gate-to-source voltage at which

(i) the surface potential FS has
thesame magnitude, but the
reverse polarity, as the bulk
Fermi potential FF.
(ii) the region near the semiconductor-
oxide interface is nearly
devoid of all mobile carriers.
(iii) the majority carrier density
near the surface increases and
the minority carrier concentration
decreases.
(iv) the majority carrier density
near the surface reduces
and the minority concentration
increases.

(c) The VGS (on) of an n –channel enhancement
kind MOSFET is

(i) less than the threshold voltage
(ii) equal to the gate-source cutoff
voltage
(iii) greater than VDS (on)
(iv) greater than VGS (th) .

(d) The speed limitations of modern
submicron logic circuits mainly stems
from the constraints imposed by

(i) the intrinsic delays of individual
gates
CPBM 8309 four Contd.
(ii) the interconnect parasitics
(iii) carrier velocity saturation
(iv) none of the above.

(e) When an n –channel depletion kind
MOSFET has ID > IDSS, it

(i) will be destroyed
(ii) is operating in depletion mode
(iii) is forward biased
(iv) is operating in the enhancement
mode.

(f) The CMOS transmission gate works
as a

(i) good pass of ’0'
(ii) good pass of T
(iii) good pass of both ‘0’ and T
(iv) bad pass of both ‘0’ and T.


(ii) Draw the circuit diagram and the corresponding
stick diagram of a CMOS inverter.

(iii) If all W/Ls are equal discuss which is
faster, a NAND or a NOR ? 2

(iv) Draw and tag the energy band diagrams
of metal, oxide and semiconductor layers
in a MOS system as 3 separate components.

(v) Write the symbol, SPICE keyword and
typical values of the Zero bias threshold
voltage and Oxide thickness of a typical
MOS Transistor. 2

(vi) describe the noise margins for MOS inverters
showing a graphical illustration. 2

(vii) For a symmetric CMOS inverter with
VT0,n = VT 0,p and kR = 1, write the
expression for VIL and VIH in terms of VDD
and VT0. 2


2. State and discuss different steps of the mask
layout design of a CMOS inverter with suitable
illustration. 10


3. (a) Write the VHDL code for a 4-bit multiplexer
where the choose Iines s0 and s1
select either input ‘‘a, b, c or d’’ to
appear on the output ‘‘x’’. 5

(b) Write the VHDL code for a positive edge
triggered d-type flip-flop. 5


4. The subsequent parameters are provided for an
nMOS process :
tox = 500 A
substrate doping NA = 1×1016 cm–3,
polysilicon gate doping ND=1×1020 cm–3,
oxide - interface fixed - charge density
Nox = two × 1010 cm3.

(a) compute the threshold voltage V T for an
unimplanted transistor. 6

(b) What kind and what concentration of
impurities must be implanted to achieve
VT = +2 V ? 4


5. compute m
PLH , t PHL , t r and t f of a inverter
with depletion load with a load capacitance of
0.11 pF. Take subsequent values for your
computations : 10
VDD = 5.0V, VOL = 0.25V, Vth,driver = 1.0V,
Vth,load = 2.0V, k driver = 25A/V2,
k load = 25 mA/V2,
W
L
W
driver L load
FHIK = 206 FHIK = 1
215
. ,
. .


6. Consider the logic circuit shown in the figure
Q-6, with VT0(enhancement) = 1.0V,
(depletion) = 3.0V and g = 0.
(a) Determine the logic function F. 2
(b) compute
W
L
L
L
such that VOL does not
exceed 0.4V. 8
5V
WL/LL
A 8/4
B 4/4 C 4/4
D 8/4
F

Earning:   Approval pending.