Biju Patnaik University of Technology 2007-6th Sem B.Tech Computer Science and Engineering COMPUTER ARCHITECTURE AND ORGANIZATION-II CLASS TEST-1 MAXKS-10 - Question Paper

ans all ques.. All ques. carry equal marks.

1.Define memory mapped I/O. provide the machine instruction used for transferring data ranging from I/O device and CPU.
2.A pipeline architecture of 3 stages S1, S2 and S3. The clock delay at every stage is: S1 take t1 cycle, S2 take t2 cycle, S3 take t3 cycle, where t1=t32. Then how many clock cycle it will take to execute 'n' instruction ?
3.What are the 4 register used in data transfer operation? Also mention the control flag of every register if they contain any.
4.How many pipeline stages are needed to perform a multiplication operation in seven bit operand CSA(Wallace tree) technique?

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