Biju Patnaik University of Technology 2007-6th Sem B.Tech Computer Science and Engineering COMPUTER ARCHITECTURE AND ORGANIZATION-II CLASS TEST-2 MAXKS-10 - Question Paper

ans all ques.. All ques. carry equal marks.

1.Name the 3 important technique used for proper synchronization ranging from the processor and I/O device
2.Draw the architectural diagram of 5 stage pipeline processor having instruction queue.
3.Define interrupt latency? Which signal is more convenient to use as interrupt request signal?
4.Reorder the subsequent set of instruction so that branch delay slot in 2 stage pipeline (IF, IE) can be used properly
LOOP shift_left R1
Decrement R2
Branch !=0 LOOP
Add R1,R3

Earning:   Approval pending.