Mahatma Gandhi University (MGU) 2006 M.Sc Electronic Science VLSI Design and Analysis - Question Paper

M.Sc. DEGREE EXAMINATION, AUGUST 2006

Second Semester

Branch : Electronics

Mech. 203 T – VLSI DESIGN AND ANALYSIS

Time : 3 Hours Maximum : 75 Marks

Part A

ans any 6 ques..
every ques. carries two marks.

1. Write an expression for the threshold voltage of MOS transistor. discuss the symbols used.
2. Sketch the current versus input voltage curve for CMOS inverter.
3. What is meant by native transistor?
4. discuss a model for dynamic register.
5. Distinguish ranging from Moore and Mealy machines.
6. Sketch the twin tub structure.
7. describe sheet resistance.
8. elaborate the advantages of CMOS process over bipolar?
9. discuss body effect.
(6 X two = 12 marks)

Part B

ans any 3 ques..
every ques. carries five marks.

10. What is latch up issue in CMOS? How is it remedied?
11. Sketch a scheme to implement OR gate using transmission gates.
12. Sketch the circuit of CMOS based half adder and corresponding stick diagram.
13. Draw the block diagram of OM system and discuss its various parts.
14. What is the significance of ?-based design rules? discuss the rules for wires.
(3 X five = 15 marks)

Part C

ans all ques..
every ques. carries 12 marks.

15. (a) explain the effects of scaling in CMOS process.
Or
(b) define the p-well and n-well processes. Compare them.
16. (a) discuss the structure of PLA. How is it implemented with CMOS?
Or
(b) discuss the implementation of CMOS based D flip-flop.
17. (a) discuss the diffusion process. elaborate the different parameters involved in this?
Or
(b) explain the functions and limitations of interconnects in chip design.
18. (a) Sketch the V-I curve for MOSFET. discuss the various regions of operation and the parameters involved.
Or
(b) With suitable models, analyze the various kinds of delays introduced by the CMOS inverter.
(4 X 12 = 48 marks)

Earning:   Approval pending.