Janardan Rai Nagar Rajasthan Vidyapeeth 2005 M.Tech Computer Science MSVD03-VERNILOG HARDWARE DESCRIPTION LANGUAGE - Question Paper

MASTER OF TECHNOLOGY

(SEMESTER - IV )(ELECTRONICS TELECOMMUNICATION/COMPUTER)


(SPL-4:VLSI DEIGN & EMBEDDED SYSTEM)

MSVD03-VERNILOG HARDWARE DESCRIPTION LANGUAGE


TIME: 03 HOURS MAX. MARKS: 75

GENERAL INSTRUCTIONS:
1. Question paper is divided into 3 groups
2. Each group is of 25 marks every
3. Figure to the right in bracket shows mark
4. Assume suitable data if necessary

GROUP A: ans any 3 ques.. ques. No. one is compulsory.
Q 1. Distingush ranging from vernilog HDL and VHDL. (5)
Q 2. Enumerate and discuss various modeling vernilog HDL. (10)
Q.3. What do you mean by operator? (10)
Q.4. Explain combinatorial UDP along with 1 example (10)
Q.5. Explain laxical conventions. (10)
GROUP B: ans any 3 ques.. ques. No. six is compulsory.
Q 6. Explain design abstraction hierarchy. (5)
Q 7 Explain difference ranging from synthesizable and behavioral modeling. (10)
Q 8. Explain parameterized modules along with 1 example. (10)
Q 9. Explain state machine kinds. (10)
Q.10. Enumerate and discuss loop statement. (10)


GROUP C: All ques. are Compulsory.
Q.11 Fill in the blanks (each ques. carries two marks)
(i) ___________________ loop is executed as long as its condition is actual.
(ii) Registers are unsigned ________________.
(iii) UDPS always have _________________ input.
(iv) Z mems _________________.
(v) String are stored in _________________.


Q.12 Multiple option ques.. (Each ques. carries two marks)
(i) Memories are arrays of :
a. Flip – flop
b. Latch
c. Registers
d. Resistors

(ii) Territory operation takes ____________________ operands.
e. One
f. Two
g. Three
h. Four
(iii) For sequential VDP, f stands for :
i. Rising edge
j. Falling edge
k. Any change
l. None
(iv) Take contains ________________ statement.
m. Single
n. Double
o. Triple
p. None
(v) Function must take _________________ time.
q. One
r. Two
s. Zero
T Four
Q.13 True or false (each ques. carries one mark).
(i) Integers are signed
(ii) Loops uses 3 expressions
(iii ) Function must return the value
(iv) Concentration can be used on 1 sides of an assignment
(v) The wait statement if it is condition is actual.

Earning:   Approval pending.